Term
| How do components exchange info? |
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Definition
standard digital commnunication interfaces establish the function and protocol of signals used to exchange between between them.
Function- data,clock, "handshacking"
Protocol: relative timing characteristics of signals in a standard interface |
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Term
| What are the two primary types of digital communication?What are the two primary types of digital communication? |
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Definition
Parallel-multiple data lines (generally one byte worth), multiple data values transmited simulataneously
Serial- Single data line, bits sent in series, one bit at a time sequentiall |
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Term
Bit rate
bit cell
BAUD rate
NRZ line code |
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Definition
bit rate- bits per second
bit cell- time to transmit a single bit
BAUD rate- bits per second
transmit value for entire bit cell |
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Term
| Synchronous vs Asynch for serial interfaces |
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Definition
synchronous= data bits read at clock edge
asynchronous= no clock; data read at preset interval(Predetermined BAUD rate) |
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Term
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Definition
Seperate- data can be transmitted and received simultaneously- full duplex- requires multiple data lines
shared- data either incoming or outgoing, half duplex, requires one data lin |
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Term
| UART-Universal asynchronous receiver/transmitte |
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Definition
| serially transmit/receive a byte (5-8 bits) of data written/stored to a register, BAUD rate must match on both sides of interface, use stop start bits to mark bytes |
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Term
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Definition
| a specific UART standard( defined voltage and timing characteristic) |
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Term
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Definition
| Transmit Data (TxD),Receive Data (RxD,and Signal Ground (SG) |
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Term
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Definition
Data written to UARTO_DR_R, passes through 16 element FIFO, permits small amount of data rate matching between processor and UART
Shift clock generated from 16x clock, oermits differences in Tx and Rx clocks to be reconciled |
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Term
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Definition
RXFE is 0 when data are avaiable
RXFF is 1 when FIFO is full |
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Term
| FIFO control has four control bits |
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Definition
BE- set when Tx signal held low for more than one from
OE- set when FIFO is full and new frame has arrived
PE- set if frame parity error
FE set if stop bit timing error |
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Term
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Definition
| buffering or temp storage method in which the entity that first exits is the one that first entered, theraby the entity served is the one that waited the longest period of time |
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Term
| SSI(Synch serial interface) signals |
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Definition
SCLK—Serial Clock (output from master)
MOSI/SIMO—Master Output, Slave Input
MISO/SOMI—Master Input, Slave Output
SS- slave select (active low) Output from master, multiple select lines for multiple slave decides |
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Term
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Definition
Pros- Full duplex communication, higher throughput than I2C or SMBus, complete protocol flexibility for bits transfered, uses only four pins( much less than parallel interfaces), at most one unique bus signal per device, extremely simple hardware interfacing( lower power than I2C or SMBus, slaves use the masters clock so no need for precision oscillators)
disadvantages- requires more pins on IC packages than I2C, only handles short distances, supports only one master device, no hardware slave acknowledgement( master could be talking to nothing and not know), no hardware flow control, prone to noise spikes, validating conformance isnt possible |
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Term
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Definition
Analog-between 0v and VDD
digital- o or 1(0v or VDD) |
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Term
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Definition
| Input device allowing humans to input binary information |
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Term
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Definition
resistor tied to VDD- negative logic,
switch open- input is high (pulled up by resistor)
switch closed input is low (pulled down through switch) |
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Term
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Definition
Resistor tied to ground- positive logic
switch open- input is low(pulled down by resistor)
switch closed- input is high(pulled up through switch) |
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Term
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Definition
high: actviated at 1 otherwise-> hiZ(open)
low: activated->, otherwise hiZ |
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Term
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Definition
multi master serial single ended computer bus
uses only two bidirectional open drain lines
serial data line (SDA) and serial clock (SCL) which both pulled up resistors.
Starts when SDA is pulled low while SCL stays high |
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Term
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Definition
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Term
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Definition
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Term
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Definition
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Term
| Master slave: Independant, Ring |
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Definition
Independant: central master connected to every slave
Ring(Daisy Chain): a ring has nodes connected everything in a circle each node has a reciever and a transmitter |
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Term
which are Synch Asynch?
UART
SSI
I2C |
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Definition
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Term
| Design a connected six digital peripheral device using an SSI that has synch serial inputs and outputs, each with a enable select pin |
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Definition
SCLK, MOSI, MISO, SS1, SS2, SS3, SS4, SS5, SS6
This has 9 signals |
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