Term
| memory is a ______________ bottleneck for servers |
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Definition
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Term
| cache memory is _____, ______, and _____ capacity |
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Definition
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Term
| disks are ______, ______, and _______ capacity |
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Definition
| slow, inexpensive and high capacity |
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Term
| main memory (RAM) acts as a bridge in terms of speed between what two subcomponents? |
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Definition
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Term
| virtualized servers generally require ________ of RAM each |
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Definition
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Term
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Definition
| dynamic random access memory |
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Term
| SDRAM stands for, and what does the S mean exactly? |
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Definition
| synchronous DRAM, synchronous means it operates in sync with the system clock for reads/writes |
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Term
| the capacity of DRAM chips is measured in |
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Definition
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Term
| ECC stands for and performs what function |
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Definition
| Error checking/correcting code, it can correct 1 bit errors and detect 2 bit errors |
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Term
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Definition
| capacity of DRAM chips X # of DRAM chips |
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Term
| the 3 capacities of DRAMs are.. |
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Definition
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Term
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Definition
| 64 bits of data (a cache line) |
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Term
| in SDRAM, the first address is supplied by... |
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Definition
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Term
| SDRAM increments a _________ to indicate the next available memory location |
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Definition
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Term
| SDRAM uses its internal clock to _____ |
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Definition
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Term
| SDRAM uses the system clock to ________ |
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Definition
| increment its address pointer |
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Term
| registered DIMMs isolate the _________ from __________, lightening the ______ |
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Definition
| memory controller, DRAM, electrical load |
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Term
| the max clock speed of DDR memory is |
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Definition
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Term
| DDR memory operates at ____ and ____ VDC |
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Definition
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Term
| DDR has a __________ prefetch |
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Definition
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Term
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Definition
| memory fetches X sets of 64 bits of data at a time |
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Term
| DDR2 requires a ___________ FSB |
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Definition
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Term
| DDR2 functions at _________ VDC |
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Definition
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Term
| DDR2 has ________ prefetching |
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Definition
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Term
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Definition
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Term
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Definition
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Term
| DDR and DDR2 actually have the _________ throughput at the same frequency |
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Definition
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Term
| Even though DDR2 has a worse latency than DDR, DDR2's ___________ can be much higher than DDR, making it faster in the end |
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Definition
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Term
| DDR3 operates at _________ VDC |
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Definition
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Term
| DDR3's memory bus operates at _______ the memory core |
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Definition
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Term
| is DDR3 backwards compatible w/ DDR2? |
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Definition
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Term
| DDR3 contains __________, which aid in the process of maintaining a server's thermal limits |
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Definition
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Term
| DDR3 works best with the __________ number of DIMMs per channel |
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Definition
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Term
| unbuffered DIMMs operate in a __________ |
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Definition
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Term
| FB-DIMMs operate in a ____________ |
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Definition
| serial PTP links topology |
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Term
| FB-DIMM has a ________ latency than unbuffered DIMM, but has greater ____________ due to the lighter electrical load |
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Definition
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Term
| every memory request must ____________ ____________ the serial linkage before returning to the memory controller in FB-DIMM setups, which increases latency |
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Definition
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Term
| FB-DIMM can support up to ______ DIMMS |
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Definition
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Term
| FB-DIMM operates at ________ VDC |
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Definition
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Term
| the AMB is responsible for... |
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Definition
channel/memory req's handling
forwarding mem requests to other AMB's
detection/reporting of errors |
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Term
| southbound frames are for _______ processes and northbound frames are for ________ processes |
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Definition
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Term
| FB DIMM has a _______ latency compared to unbuffered DDR2 RAM, in which __________ increases as DIMMs are added |
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Definition
constant, latency
this is why FB DIMM is more scalable |
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Term
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Definition
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Term
| metaRAM is used with _______ and _______ DIMMs |
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Definition
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Term
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Definition
| allows multiple SDRAMs to appear as a single, large capacity SDRAM |
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Term
| since metaRAM lightens the electrical load, DIMMs in this setup are allowed to run at ________________ frequencies |
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Definition
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Term
| metaRAM can deliver _________ times the regular amount of server memory capacity b/c of ______________ |
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Definition
| 2-4x, lightened electrical load |
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Term
| unfortunately, metaRAM went _________ so this technology is no longer in use |
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Definition
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Term
| what is memory interleaving? |
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Definition
| divides memory/cache lines up between 2 or more DIMMs to increase performance, as more than 1 line can be accessed at a time because they are potentially held by different DIMMs |
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Term
| two common interleaving setups are |
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Definition
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Term
| in a 2 DIMM interleaving array, one DIMM could hold only the _________ addresses and the other could hold only the ___________ addresses |
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Definition
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Term
| 4 way interleaving is able to transfer ______ as much data per memory access as 2 way interleaving |
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Definition
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Term
| two way interleaving has a ________ bit bus, and 4 way interleaving has a _________ bit bus |
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Definition
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Term
| after first access latency in interleaved setups, all memory addresses in DIMMs requested are transferred in __________, w/o _________ |
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Definition
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Term
| interleaving used to be _________ configurable but is now handled exclusively by ________ |
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Definition
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Term
| CUCSEM stands for and performs which function |
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Definition
cisco unified computing system extended memory
its essentially the same deal as metaRAM |
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Term
| server demands are driven by |
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Definition
64 bit applications
operating systems
virtualization |
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Term
| adding ___________ is the most cost effective way to improve web server and database server performance |
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Definition
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Term
| a typical virtualized server uses |
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Definition
2 xeon 5500 processors
2-4GB of DDR3 per virt. machine
has 36GB of total memory |
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Term
| CUCSEM uses 2 things, which are |
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Definition
the quad core xeon 5500 and
ASICs, application specific integrated circuits |
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Term
| __________ is placed between the processor and DIMM, its role is to ... |
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Definition
ASIC
increases memory capacity |
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Term
| a dual socket machine using CUCSEM supports ___________ of memory |
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Definition
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Term
| why is the 5500 processor a good idea in environments which require a shitload of RAM? |
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Definition
built in mem controller
3 channels of memory (DDR3)
each core has dedicated system memory
cost effective |
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Term
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Definition
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Term
| 2 primary aspects of memory performance |
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Definition
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Term
| BW is calculated as... (recite the equation) |
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Definition
size of channel in bytes (multiplied by)
# of channels (multiplied by)
frequency of memory |
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Term
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Definition
frequency
number of channels
size of channels |
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Term
| latency can be defined as |
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Definition
| the number of FSB clock cycles needed to retrieve a cache line |
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Term
| mem addresses are divided equally into |
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Definition
| column addresses and row addresses |
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Term
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Definition
| which page of memory an address is in |
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Term
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Definition
| the location on the page of memory the address is actually in |
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