Term
| in a server, the chipset defines the operation of at least |
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Definition
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Term
| increased cache size causes slower main memory access because... |
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Definition
the processor takes longer to search the cache for data and the order that data is searched for goes
registers, cache, ram, disk |
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Term
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Definition
cycles per instruction
the number of clock cycles required to execute an instruction |
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Term
| what 2 things can be done to improve system performance from a chipset standpoint |
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Definition
1) decreasing CPI
2) raising clock rate |
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Term
| the CPU relies on the chipset to quickly... |
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Definition
| transfer information from the main memory |
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Term
| the most frequently accessed shared resource in a computer is |
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Definition
| RAM, because of this, it also has the highest latency |
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Term
| in terms of a chipset, hardware scalability is determined by... |
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Definition
| how efficiently multiple CPUs can share memory |
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Term
| ________________ accelerate CPU access to memory, but limit multi processor scalability |
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Definition
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Term
| two commonly used multi-processor chipset architectures are... |
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Definition
NUMA (non uniform memory addressing)
SMP (symmetric multi processing) |
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Term
| which is more scalable, NUMA or SMP? why? |
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Definition
| NUMA b/c in SMP all processors wait for resources in the same queue |
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Term
| in NUMA, processors have access to ... in terms of memory |
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Definition
| local/near memory, and remote memory |
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Term
| groups of processors are connected by which two technologies made by intel and AMD? |
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Definition
hypertransport for AMD
scalability ports for intel xeon systems |
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Term
| AMD's version of NUMA is called |
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Definition
| SUMO: sufficiently uniform memory organization |
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Term
| local memory to one processor in a processor group is ______ memory to another process in the same group |
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Definition
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Term
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Definition
| the number of processors which can access local memory |
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Term
| in NUMA, remote memory can be accessed by a CPU but ... |
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Definition
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Term
| requests between local and remote memory use ... |
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Definition
| scalability ports or hypertransport links |
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Term
| in AMD's SUMO architecture, each CPU uses _____ hypertransport links, for what? |
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Definition
3
two for CPU-CPU linkage
one for I/O linkage |
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Term
| hypertransport allows ____ CPU's to be directly connected and ____ CPU's to be indirectly connected but no more than ____ hops away |
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Definition
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Term
| when would remote memory be used in a multi processor architecture? |
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Definition
| when queues are so large on local/near memory that the latency to get to the remote memory is worth it |
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Term
| when would remote memory be used in a multi processor architecture? |
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Definition
| when queues are so large on local/near memory that the latency to get to the remote memory is worth it |
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Term
| what assists remote memory access in multi processor architectures? |
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Definition
| the SRAT, static resource affinity table |
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Term
| the SRAT stores information such as |
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Definition
local memory for each processor
number of processors |
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Term
| the SRAT is stored in...and is read by ... on boot |
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Definition
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Term
| NUMA works well for the following operating systems |
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Definition
w2k3/8 ent
w2k3/8 DC
linux 2.6 and up |
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Term
| in SMP, system resources are all ______ by the multiple processors |
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Definition
| shared, which increases queue times |
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Term
| the caches of each CPU in an SMP architecture must be kept ______, which is where the _____ protocol comes in |
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Definition
coherent
MESI (modified, exclusive, shared and invalid) |
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Term
| CPU's use ___________ in SMP architectures during every read/write to memory to ensure coherency between caches |
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Definition
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Term
| for each data request by a CPU, there is a broadcast to all other processors to see if the requested data is in their caches, which is called a |
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Definition
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Term
| explain the 4 states of data in CPU cache according to the MESI protocol |
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Definition
modified - data exists in cache and has been modified
exclusive - data exists in only one cache
shared - data is in more than one cache
invalid - data has been modified by a write to the cache |
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Term
| what is AMD's version of MESI? |
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Definition
MOESI
has one more data flag, "owner"
when a CPU needs to read updated data it reads the data from the "owner"'s cache |
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Term
| snoop overhead increases as a result of what 2 things |
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Definition
number of CPU's increases
cache size increases |
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Term
| intel's FSB protocol is limited to _____ processors |
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Definition
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Term
| a solution to the latency issues associated with snoop cycles is... and what does it do exactly |
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Definition
cache coherency filter
checks if address is even in remote caches before snoop cycle has begun
if no address found in filter, no snoop cycle begun |
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Term
| UEFI is a replacement to IBM server ____ |
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Definition
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Term
| in terms of applications, what must be able to handle multiple processors |
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Definition
| the coding must be able to generate the amount of the threads that the multiprocessor architecture is able to handle or the benefits of multiple processors are sort of void |
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Term
| in general not many applications scale well beyond ____ core processors |
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Definition
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Term
| ____________ servers can often take advantage of multiple CPUs |
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Definition
| database and application servers |
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Term
| database and application servers can expect up to a ________ increase in performance with a second processor |
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Definition
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Term
| NUMA systems show good scalability up to |
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Definition
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