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DDR-200
Module
Memory Speed
Bus Speed |
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DDR-266
Module
Memory Speed
Bus Speed |
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DDR-333
Module
Memory Speed
Bus Speed |
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Term
DDR-400
Module
Memory Speed
Bus Speed |
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Term
DR-500
Module
Memory Speed
Bus Speed |
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Term
DDR2-400
Module
Memory Speed
Bus Speed |
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Term
DDR2-533
Module
Memory Speed
Bus Speed |
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Term
DDR2-667
Module
Memory Speed
Bus Speed |
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Term
DDR2-800
Module
Memory Speed
Bus Speed |
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Term
DDR2-1066
Module
Memory Speed
Bus Speed |
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Term
DDR3-800
Module
Memory Speed
Bus Speed |
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Term
DDR3-1066
Module
Memory Speed
Bus Speed |
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Definition
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Term
DDR3-1333
Module
Memory Speed
Bus Speed |
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Term
DDR3-1600
Module
Memory Speed
Bus Speed |
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100MHz for Memory Clock Speed
(3 modules) |
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Term
133MHz for I/O & Memory
(3 modules) |
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Definition
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Term
166MHz for I/O & Memory
(3 modules) |
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250MHz for I/O & Memory
(2 modules) |
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Term
| What is the maximum number of chips on a non-ECC DDR module? |
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Definition
| 32 (8 without parity x 4) |
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Term
| To run a computer in a dual-channel mode a pair of DDR modules must match in 4 things: |
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Definition
Capacity (e.g. 1024MB)
Speed (e.g. PC-5300)
Number of chips & sides (e.g. 2 sides with 4 chips/side)
Matching size of rows & columns |
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Term
| Formula to calculate the data transfer rate of a DDR = |
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Definition
clock rate x 2 x 64bits
__________________________
8bits/byte |
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Term
| (T/F) It is not possible to use DDR in a dual channel configuration. |
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Definition
| False, the two technologies are independent, but many motherboards use both with DDR memory in a dual channel configuration. |
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Term
| What was a solution to memory bottlenecks produced following increases in processor speed and performance? |
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Definition
| The use of dual channel architecture relieved the bottleneck at the memory controller by doubling the available bandwidth going to the CPU. |
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Term
What type of RAM is a DIMM?
**041 |
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Definition
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Term
| When is it appropriate to use a 1GB high density DDR matrix of 128Mx4? |
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Definition
| Only when used on specific servers. |
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Term
| What is the matrix configuration of an ECC module, and what is the ratio of DDR:chip? |
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Definition
| x4 with a factor of 9, and can occupy either one side of the module, or both sides of the module. |
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Term
(T/F)
Triple channel RAM allows for access to 6 RAM modules at one time. |
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Definition
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Term
| For DDR, there are normally 4 _____ and only 1 _____ can be active in each. |
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Definition
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Term
| What is the maximum number of chips on a DDR module with ECC? |
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Definition
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Term
| 64Mx8 chips are mainly used in desktops and notebooks, but are making entry into the ______ market. |
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Definition
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Term
| What chip matrix constitutes a low density 1GB DDR, which can be recognized by nearly all motherboards? |
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Definition
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Term
| What happens when the I/O speeds are greater than memory speeds? |
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Definition
| There is a bottleneck effect at the memory controller. |
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Term
| What is meant by the DDR chip notation, 64Mx8? |
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Definition
| The density of the chip can be calculated in megabits (Mbit) or megabytes (MB) knowing that the matrix is composed of 64 million 8-bit storage locations. |
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Term
| How is the physical matrix of a memory chip defined? |
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Definition
| The size of the matrix is calculated from the product of the number of banks, rows, and columns used to arrange the x-bit storage units, where x = a factor of 4. |
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Term
| What are the requirements for a dual-channel architecture? |
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Definition
| A dual-channel-capable motherboard, and two or more memory modules such as DDR, DDR2 SDRAM, or DDR3 SDRAM. |
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Term
| How does dual channel architecture relieve memory bottlenecks? |
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Definition
| By doubling the available bandwidth going to the CPU. |
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Term
| What is the reason for combining DDR chips into DIMM/SODIMM modules? |
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Definition
| To increase memory capacity and bandwidth. |
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Term
| What is meant by the DDR chip notation, 64Mx4? |
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Definition
| It describes the density of the chip in megabits indicating that the chip matrix is composed of 64 million 4-bit storage locations. |
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Term
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Definition
| Double data rate where each memory module is accessed twice per clock cycle. |
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Term
RAM acts as a ______ between the hard drive and the _____.
**026 |
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Definition
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Term
What was the reason for introducing DIMMs into the RAM market?
http://en.wikipedia.org/wiki/Dimm |
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Definition
| Since Intel's Pentium has (as do several other processors) a 64-bit bus width, it requires SIMMs installed in matched pairs in order to complete the data bus. The processor would then access the two SIMMs simultaneously. DIMMs were introduced to eliminate this practice. |
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Definition
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Term
| How are a DIMM's capacity and timing parameters identified? |
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Definition
| Using the serial presence detect (SPD) chip which contains information about the module type and timing for the proper memory controller configuration. |
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Term
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Definition
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Term
| What is the most common form of a clock signal for electronic circuits? |
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Definition
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Term
| An ideal ______ _____ alternates regularly and instantaneously between two levels. |
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Definition
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Term
| The ratio of the high period to the total period of a square wave is called the _____ _____. |
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Definition
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Term
| The difference between the upper and lower frequencies in a contiguous set of frequencies. |
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Definition
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Term
| a band of a given width can carry the same amount of information, regardless of where that band is located in the _______ _______. |
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Definition
information
frequency spectrum |
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Term
| In computer networking and other digital fields, the term bandwidth often refers to a ______ ______ measured in ______. |
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Definition
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Term
| For bandwidth as a computing term, less ambiguous terms are (5): |
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Definition
bit rate
throughput
maximum throughput
goodput
channel capacity. |
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Term
| according to _______ _____, the digital data rate limit (or channel capacity) of a physical communication link is proportional to its bandwidth in hertz, sometimes denoted radio frequency (RF) bandwidth, signal bandwidth, frequency bandwidth, spectral bandwidth or analog bandwidth. |
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Definition
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Term
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Definition
| each memory channel accesses two RAM modules simultaneously |
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Term
| In double pumping, each clock edge is referred to as a "_____", with two ____ per cycle. |
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Definition
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Term
| How many beats per cycle are there in double pumping, and what are they called? |
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Definition
2 beats/cycle
upbeat
downbeat |
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Term
| DDR SDRAM popularized the technique of referring to the bus bandwidth in _______ ____ ______, the product of the transfer rate and the bus width in bytes. |
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Definition
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Term
| Transfer Rate x Bus Width |
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Definition
| Bus Bandwidth in xbytes/second |
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Term
| DDR SDRAM operating with a 100 MHz clock is called _________(after its 200 MT/s data transfer rate) |
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Definition
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Term
| A 64 bit (8 byte) wide DIMM operated at 200 MT/s is called _________. |
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Definition
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Term
| What does the 1600 stand for in PC1600? |
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Definition
| after its 1600 MB/s (theoretical) peak bandwidth |
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Term
| 800 MHz clock _______ is called PC3-12800 |
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Definition
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Term
| _______ is simply how many times per clock cycle data is being transmitted. |
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Definition
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Term
| _______ transmits data on only the rising edge of the clock |
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Definition
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Term
| data is transmitted both rising and falling edges |
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Definition
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Term
double pumping
+
internal clock is run at half the speed of the data bus |
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Definition
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Term
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Definition
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Term
With data being transferred 64 bits at a time, DDR2 SDRAM gives a transfer rate of:
100MHz(memory clock rate)
×
2 (for bus clock multiplier)
×
2 (for dual rate)
×
64 (number of bits transferred)
divided by
8 (number of bits/byte). |
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Definition
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Term
| The best-rated _____ memory modules are at least twice as fast as the best-rated ____ memory modules |
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Definition
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Term
(T/F)
The key difference between DDR and DDR2 is that for DDR2 the memory cells are clocked at 1 quarter (rather than half) the rate of the bus. |
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Definition
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Term
| The DDR2 _______ ______is 4 bits deep, whereas it is two bits deep for DDR and eight bits deep for DDR3. |
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Definition
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Term
| _______ are identified by their peak transfer capacity (often called bandwidth). |
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Definition
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Term
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Definition
| data transfer rate for raw DDR chips |
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Term
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Definition
| theoretical bandwidth with the last two digits truncated and is used to describe assembled DIMMs |
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Term
| How is DDR2 bandwidth calculated? |
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Definition
take the transfers per second and multiply this by 8
given 64 bit bus which equates to 8 bytes of data per transfer |
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Term
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Definition
| by adding an extra data byte lane used for correcting minor errors and detecting major errors for better reliabilty |
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Term
| What does the R mean in PC2-4200R? |
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Definition
| That the module is registered or buffered to improve signal integrity, but also increased latency |
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Term
| The highest rated DDR2 modules in 2009 operate at 533MHz (1066MT/s) compared to the highest rated DDR modules operating at _____MHz (_____MT/s) |
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Definition
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Term
| The primary benefit of DDR3 SDRAM over its immediate predecessor, DDR2 SDRAM, is its ability to transfer data at twice the rate (________), enabling higher bandwidth or peak data rates. |
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Definition
| eight times the speed of its internal memory arrays |
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Term
| With ____ transfers per cycle of a ______ clock, a 64-bit wide DDR3 module may achieve a transfer rate of up to 64 times the memory clock speed in megabytes per second (MB/s). |
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Definition
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Term
With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of:
100MHz (memory clock rate)
×
4 (for bus clock multiplier)
×
2 (for data rate)
×
64 (number of bits transferred)
divided by
8 (number of bits/byte) |
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Definition
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Term
| DDR3 standard permits chip capacities of up to ____ _______. |
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Definition
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Term
Voltages supplied to:
DDR
DDR2
DDR3 |
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Definition
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Term
| The main benefit of DDR3 comes from the higher bandwidth made possible by DDR3's 8-burst-____ ______ ______, in contrast to DDR2's 4-burst-deep or DDR's 2-burst-____ ________ ________. |
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Definition
deep prefetch buffer
deep prefetch buffer |
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Term
prefetch buffer
DDR
DDR2
DDR3 |
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Definition
2 burst-deep
4 burst-deep
8 burst-deep |
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