Term
| Software execution speed verses I/O hardware |
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Definition
software executes at MHz (μsec) speeds
I/O hardware operates at msec-sec speeds |
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Term
interfacing software & I/O hardware
requires ____ |
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Definition
synchronization
•coordination of timed events |
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Term
| I/O Device Hardware “States” |
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Definition
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Term
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Definition
device is disabled or inactive
no I/0 in idle state |
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Term
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Definition
| Device is actively performing task and is unable to perform a new task yet, will set a flag when task is complete |
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Term
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Definition
| device is active and awaiting new task |
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Term
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Definition
| Elapsed time between start and end of some operation (Clicking on a link vs link opening) |
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Term
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Definition
| System with bounded latency, system will respond within a given time limit |
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Term
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Definition
| Max data flow possible (bytes/sec |
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Term
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Definition
| actual rate of data processing or operation completion |
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Term
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Definition
| order of service when two or more simultaneous service requests are possible |
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Term
| Methods for synchronizing software to I/O(peripheral) hardware. |
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Definition
Blind Cycle
Busy wait
Interrupt(IRQ)
Periodic polling
Direct Memory access (DMA) |
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Term
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Definition
| Wait fixed time for I/O to finish its job (Software delay loop) |
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Term
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Definition
| software loop checks flag to know when I/O job is finished |
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Term
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Definition
hardware generated break in software execution, Asynchronous communication between processor and peripheral hardware
Inputs- Requests IRQ when new data is available (Interrupt service routine ISR stores new input data to memory)
Output devices- Request IRQ when output is idle" Give me more data to send out" |
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Term
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Definition
Use Clock Interrupt (SysTicktime) to periodically check I/O status via flag
for tasks that demand interrupt but I/O device does not have a direct interrupt |
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Term
| Direct Memory access (DMA) |
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Definition
| Uses a DMA controller to transfer memory values from input devices or to output devices without software assistance, DMA synchronization allows high bandwidth and low latency. |
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Term
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Definition
| Break in normal program flow Reset Non maskable interrupt(NMI) Faults Interrupts |
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Term
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Definition
When exceptions occur they are managed by blovks of code written to handle each individual exception
Fault handlers
System handlers (NMI and other)
Interrupt service routines(ISR and all interrupts)
address of each handler is stored in ROM at pre-set Vector address |
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Term
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Definition
| Power on reset or forced external reset, restart programming execution from begginging of code |
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Term
| Non Maskable interrupt (Nmi) |
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Definition
| Always active interrupt, (external NMI pin) |
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Term
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Definition
| Error detected during program execution( hard(unknown), memory,bus,usage |
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Term
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Definition
| ARM specific exceptions( SysTick which isnt peripheral block) |
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Term
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Definition
| Break normal program flow, execute Hander/ISR, return to normal program flow |
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Term
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Definition
| Each exception has a unique vector address in ROM which contains address of full handler/ISR |
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Term
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Definition
| Trigger, thread, arm(disarm), flag, global interrupt enable |
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Term
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Definition
| Asynch hardware event that causes an interrupt |
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Term
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Definition
| Path of action for software execution, unique register values and variables for each side. ISR is a background thread. |
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Term
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Definition
| To enable or disable an interrupt source, a trigger, each interrupt source has an arm bit |
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Term
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Definition
| Hardware generated bit that indicates if an exception has occured, readable by software and is typically reset by writing to the flag bit (cleared by ISR/Handler |
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Term
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Definition
| System wide control bits to enable disable all interrupts from generating flags. |
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Term
Hard interrupts are____
Exceptions faults software interrupts are____ |
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Definition
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Term
| Interrupt service routine (ISR) |
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Definition
| Subroutine which processor is forced to execute to respond to a specific event |
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Term
| Steps hardwired in the CPU to occur when an exception occurs |
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Definition
1.Finish current instruction
2.Push CPU registers onto stack
3.Switch to handler/privileged mode
4.Load PC with address of exception handler
5.Load LR with EXC_RETURNcode
6.Load IPSR with exception number
7.Start executing code in exception handler |
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Term
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Definition
| Main stack pointer available in thread mode and handler mode |
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Term
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Definition
| Process stack pointer,only available in thread mode |
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Term
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Definition
| Lowest IRQ# has highest priority |
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Term
PRIMASK
PM=1
PM=0
assembly instructions used to set/clear PRIMASK? |
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Definition
exception Mask register, PM=1, global disable of configurable exceptions
pm=0 enable conf exceptions, pm=0 on reset
CPSID, sets primask PM to 1 disable
CPSIE- Sets primask PM to 0 enable |
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Term
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Definition
| defines privilege and stack |
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Term
| Control mode that defines execution privilege in thread mode |
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Definition
nPRIV,bit[]
0 thread mode has privileged access
1, has unprivileged access |
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Term
| CONTROL that defines current stack |
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Definition
SPSEL,bit[]
0 Use SP_Main(MSP) as current stack
1 Use SP_Process(PSP) as current stack in |
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Term
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Definition
| nested vectored interrupt controller, takes control during handler mode, automates action to minimize IRQ latency, manage multiple interrupts |
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Term
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Definition
| Interrupt Set-Enable Register- WRITE 1 TO enable policy |
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Term
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Definition
| Interrupt Clear Enable Register, write 1 to clear polocu |
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Term
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Definition
| used for back to back interrupts- next IRQ chained to the tail of last IRQ |
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Term
| Ports that support interrupts |
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Definition
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Term
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Definition
| Bit 24 0= none 1= interrupt; writes 1 to reset ISF |
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Term
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Definition
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Term
| What do you write to clear interrupt flag? |
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Definition
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Term
| What are the three conditions that must be true for an interupt to occur? |
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Definition
1) Enable: interrupts globally enable, I=0 in PRIMASK
2) ARM: control bit for each possible source is set
3)Trigger: Hardware action sets source specific flag |
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Term
| What happens if you dont clear trigger flag? |
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Definition
| you will get endless interrupts |
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Term
| provides asynchronous communication with peripheral devices |
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Definition
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Term
has highest priority other
than Reset |
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Definition
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Term
| How would an ASM program implement a global disable of all peripheral interrupt sources? |
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Definition
| CPSID I (DISABLE ALL MASKABLE PERIPH interrupt sources) |
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Term
What is the function of the Nested Vectored Interrupt Controller
within the ARM controller? |
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Definition
| The NVIC manages tasks during Handler mode including automated interrupt actions such as preserving the CPU state, negotiating interrupt priority, and tail-chaining of multiple interrupt sources. |
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Term
Discuss the impact, or limitations, of choosing a serial communication standard with a shared receive
and transmit line |
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Definition
| A shared Rx/Tx line minimizes the number of signals/wires needed but eliminates the opportunity to simultaneously transmit and receive. |
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