Term
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Definition
| Core of a microcontroller |
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Term
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Definition
outside of the core, I/O devices
GPIO
Timers
interrupt controller
communication ports
A/D converter |
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Term
| Peripheral units composed of |
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Definition
Function hardware- counters for timers,packet framing circuits for communication ports
Config Registers- addressable memory to set how function hardware behaves
data registers- data bytes to/from communication ports,timer values, ADC values
all of these are memory mapped |
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Term
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Definition
| Each register has a unique address in the controller memory space so it can be read/written |
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Term
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Definition
physical contact on the controller package that connects to peripheral functions
permits interface to outside world can be input, outputs or both |
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Term
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Definition
| Collection of several pints that can be addressed as a unit |
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Term
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Definition
| To minimize package pins, most ports serve multiple functions |
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Term
| PCR (pin control register) |
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Definition
| sets alternate pin functions set by MUX bits in the PCR |
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Term
| PCR registers to pin, to port, how many global pin registers and ISFR |
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Definition
| one register for each pin, 32 registers for each port, 2 global. pin control registers (allow simulataneous, config of PCR registers) one ISFR |
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Term
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Definition
| Interupt status flag pin 24 0=none 1= interrupt; write to reset |
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Term
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Definition
| pin mux control select alt function for each pin (10:8) |
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Term
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Definition
| Drive strength enable 0=low, 1= high strength |
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Term
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Definition
| Pull enable, pullup/down resistor- 0 disable, 1= enable |
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Term
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Definition
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Term
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Definition
1) read current value from config register
2) modify only the bits you want to set using (ORRS) or clear (BICS)
3)WRITE modified value back to config register |
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Term
| Configuring gpio requires 3 steps |
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Definition
1)Enable port clocks- disabled by default (SIM_SCGC5) controls clocks to ports A-E
2)set pin function to GPIO using PCR- Config Multi tasking port to the GPIO function
3)Set pin data direction- pins can be input or output as determined by PDDR |
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Term
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Definition
Enables output to physical pin,each port has one register for data direction
each ddr has one bit for direction of each pin
0= INPUT
1= OUTPUT |
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Term
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Definition
latch that holds data to be output to each pin if PDDR=1
Config logic level on output pins of port |
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Term
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Definition
Set output
0= bits in PDOR dont change
1= bits in pdor set to logic 1 |
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Term
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Definition
Clear output
0= do not change
1= clear to logic 0 |
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Term
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Definition
Toggle output
0= do not change
1= set to inverse of current logic |
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Term
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Definition
stores value on each pin of a port
Data input
0= logic 0
1= logic 1 |
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