Term
| Advantages and disadvantages of ASICs |
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Definition
Advantages:
- very high performanc and efficient
Disadvantages:
- not flexible (can’t be altered after fabrication)
- High NRE Cost |
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Term
| Advantages and disadvantages of software |
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Definition
Advantages:
- software is very flexible to change
Disadvantages
- performance can suffer if clock is not fast
- fixed instruction set by hardware |
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Term
| Advantages of reconfigurable computing |
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Definition
Advantages:
• fills the gap between hardware and software
• much higher performance than software
• higher level of flexibility than hardware |
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Term
| What is spatial and temporal based computing? |
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Definition
Temporal-based execution (hardware)
- parallel computations
Spatial-based execution (software)
- sequential computations
- slower than ASIC but might be faster than FPGA
Extract parallelism (or concurrency) from algorithm descriptions is one of the keys to acceleration using reconfigurable computing
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Term
| Frequency and power comsuption of ASIC/ASIP |
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Definition
1-2 GHz
feq thenths of watts |
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Term
| Frequency and power comsuption of reconf. HW |
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Definition
xilinx v7 (28nm)
20-30 W
Up to 600MHz
Xilinx Artix-7 (28 nm)
4-8W
500MHz |
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Term
| Frequency and power comsuption of Multicores and GPUs |
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Definition
IBM cell (90nm)
40-50 W
3.2 GHz
Nvidia Geforce GFX 560 ti (40nm)
170 W
0.8 GHz |
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Term
Frequency and power comsuption of GPP
(general purpose processors) |
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Definition
Xeon 7560 (45 nm)
130 W
2.26 GHz
i7E 3960X (32 nm)
130 W
3.3 GHz |
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Term
| Frequency and power comsuption of mobile processors |
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Definition
Atom z6xx (45 nm)
1.3-3 W
400 MHz
Apple A5 (45 nm)
1.9W
1 GHz |
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Term
| Which processor type is the most efficient? |
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Definition
depends on the application
Performance?
energy comsumption?
performance and energy consumption also depends on the application
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Term
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Definition
Energy is always over time
E = P*t |
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Term
| Why do we need reconfigurable computing? |
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Definition
Performance, performace/power:
- many applications run more efficently on reconf HW
* streaming applications
* parallelins
* when GPPs and ASICs dont match the applications requirements
* application with changing requirements
FPGA provide:
- spatial coomputational resources to impl. massively-parallel computations in HW
- customization
-adaption
More:
- reduce TTM
- No NRE cost vs ASIC |
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Term
| Reconf. HW application characteristics |
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Definition
Computational requirements:
- Data parallelism (few or no data dependencies)
- Data element size and aritmetic complexity
- Pipelining (can app. tolerate delay?)
- Simple Control (static vs dynamic, feed-only forward vs feed-back loops)
IO requirements:
- feed design with enough data
- memory elements to coordinate IO and computation (BRAM, LUTs, FF)
- Memory size vs memry ports (bandwidth) |
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Term
| What is FPGA the "emulation" technology mean? |
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Definition
- FPGA have a disadvantage over ASICs
ATP = (10^2)x- (10^3)x
(Area, Time, Power)
- Still for some computations FPGAs app. get 10x performace/watt (energy efficency) |
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Term
Name five ways that might make FPGA better (than ASICS?)
whay limit these five ways? |
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Definition
- Exploit parallelism
(as much as the application spec. and FPGA resources allow)
- Pipelining (flip-flips are for free)
(how much latency can the application tolerate?)
- Streaming
(streaming, data-flow vs complex control)
- Flexibility (to reconf.)
(adaption to the app. req.)
- Customization
(complete control over arithmetic schemes, and number representation) |
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Term
| How and when can an FPGA be reconfigured? |
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Definition
- Reconf. once (static, before execution)
- Runtime reconf. (dynamic, during runtime)
->global (entire device)
-> partial (part of the device)
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Term
| what can I do if my design wont fit in my FPGA? |
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Definition
research if the design can be broken into parts and swap them in and out.
although reconf. overhead...
(can I stall to reconf?)
(can I afforde the energy cost?) |
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Term
| What is guarded evaluation? |
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Definition
disconnect a part of your design with a logic guard.
experimets show sw activity reduced by 22% and power by 14%
The essential idea here is to dynamically detect on a per clock cycle basis which parts of a
logic circuit are being used and which are not. The ones that are not can then be shut off. This is done
by ensuring that no logic transitions propagate through this logic |
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Term
| how much energy reduction can pipelining achieve in a design? why? |
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Definition
40-90%
Keeping clock frequency constant, and introducing more pipeline stages, will reduce spurious glitches and thus dynamic power |
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Term
| what is Power-aware clustering? |
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Definition
put high-activity nets together in
the same cluster of logic cells |
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Term
| where is the largest portions of power consumed in an FPGA device? |
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Definition
1. net power (reconf. wires)
2. i/o, memory, or gate power (depending on app)
(static power is small) |
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Term
| how can we reduce FPGAs' static power? |
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Definition
- Flash switch technology
- Switch off things not used
--> multipliers dps-slices
--> Dual port BRAM
--> ripple carry chaing (70-90% unused)
--> clock generators
--> interconnects
-use ASIC technologies
--> low voltage ios
-->FF dont have an explicit load-enable |
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Term
| how can power consumption be reduced in the clock networks? |
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Definition
- clock gating
- Placement technique to reduce interconnect resource usage on the clock network |
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