Term
| how to reduce switching power? |
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Definition
– reduce supply voltage (VDD).
– reduce clock frequency (f).
– reduce signal activity (alpha).
– reduce nodal capacitance (C). |
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Term
| Why cant VDD and VT continue to decrease? |
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Definition
voltage cannot drop further because we will lose speed, static power increases and becomes the bottle neck.
sub-threshold operations possible for some devices =>frequency much lower ~ kilo hertz, eg medical device. |
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Term
| NEW transistor techniques |
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Definition
NEW - Tunnel FET
material at the gate is changed (not doped)
one of a few new techniques beeing developed, but has problems that need solving |
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Term
| name a few libraris that can be used at implemenetation |
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Definition
– High-Performance library.
– Low-Power library.
– Low (LVT), Standard (SVT), High (HVT) VTH MOSFETs. |
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Term
describe reverse and forward biasing and how
they can be used |
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Definition
Reverse body biasing (RBB)
VB < 0 V (NMOSFET)
VTH increases
leakage decreases.
Forward body biasing (FBB)
VB > 0 V (NMOSFET)
VTH decreases
higher speed.
Faulty units at fabriccation can be saved!
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Term
how can Delay Distribution of Logic
be used when designing logic? |
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Definition
Logic paths exhibit different delays.
Critical paths must satisfy clock rate constraint
Use an combination of high and low VT cells to satisfy
critical path => reduce static power
(high VT slow, low VT fast) |
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Term
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Definition
(Dynamic Voltage and Frequency Scaling)
- Aggressive VDD reduction causes timing violations!
- Implement a feedback system that regulates speed,
in the process also handling variations.
SLIDE 21 example
two flip-flops
shadow latch trigger on falling edge
if the latches trigger on different values you have lowered the VDD too much |
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Term
| Name the 9 Low-power techniques |
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Definition
Body biasing
Multi-VTH
Multi-VDD
DVFS
Operand isolation
Factoring
Encoding
Clock gating
Power gating |
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Term
| Describe Operand isolation |
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Definition
Reduce Psw by gating input signals
which are not needed
Example 32-bit multiplier where only 16-bits can
be used for some operations to save power 60% power reduction |
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Term
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Definition
Reduce Psw by reordering gates to minimize the
switched capacitance of fXCVDD^2.
assign gates in a way that the total gate switching is minimized.
XOR - bad :(
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Term
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Definition
- Encode data before bus transmission.
- Example slide 28 Bus invert coding reduces 64 trans. to 53.
two examples
right: encoding, if inv is high, use the inverse of all input data, this will reduce the switching
cost: one added wire |
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Term
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Definition
most important one!
use an and-gate, saving capacitance to switch,
clock is the most important when saving power because the clock is switching at every cycle.
drawback: add gates to clock => more delay on critical path |
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Term
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Definition
Accelerators -> reduce execution time + energy
add special purpose accelerator, the accelerator can be tured off when not in use.
Accelerators reduce energy via
execution time reductions (E = T x P).
But accelerators also increase
circuit area and, probably, power dissipation |
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Term
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Definition
Power gating will reduce static power
Use a wide transistor for "big" currents
no leakage when turned off
example: power gating the multiplier |
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Term
| Rank the design flow power savings |
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Definition
most first
1. algorithm
2. architecture
3. RTL
4. Gate
Early design decisions yield higher power reductions than late decisions.
Important for systemarchitects to know what low-power techniques can be used. |
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Term
| Which are the most significant missed low power opportunities? |
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Definition
most first
1. missed clock gating
2. inefficient design impl.
3. inefficeint arch.
4. poor local register enable conditions
5. lack of a power gating desing strategy |
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