Convert the decimal number 29.40625 into its exact equivalent binary number. 

29 base 10 = 11101 base 2 0.4062 base 10 = 0.01101 base 2 

What range of numbers can be represented by the following number systems: - 8-bit binary, one’s complement numbers.
- 8-bit binary, two’s complement numbers. 

-127 to +127 -128 to +127 

(a) Show analytically that these circuits implement the same Boolean function, i.e. that M = N. Hint: transform to SOP form and apply the consensus theorem

(b) Show the minimum SOP form for this function. Hint: use the consensus theorem

(c) Show how to implement this Boolean function (of 6 variables) using minimum number of 2- to-1 multiplexers, with no extra gates

(A′ + C)(B′E + C′) + CDF′ = A′B′E + A′C′ + B′CE + CDF′ Circuit on right
(A′ + C)(B′E + C′ + D F′) = A′B′E + A′C′ + A′DF′ + B′CE + CDF′ = A′B′E + A′C′ + B′CE + CDF′ (consensus of A′C′ and CDF′)

b) M=N=A′B′E + A′C′ + B′CE + CDF′= A′C′ + B′CE + CDF′ (consensus of A′C′ and B′CE)

C) Solution: starting with min SOP form, use C as select input for the last-stage 2-to-1 multiplexer that outputs the desired function A′C′ + B′CE + CDF′

The function for I1 = B′E + DF′ can be implemented using just three 2-to-1 multiplexers (see below). So the optimal implementation has four multiplexers.

Other)[image] 

(a) Implement the function f(A, B, C, D) = Σ m(1, 3, 7, 11, 14, 15) using a two-level, NOR-NOR circuit using a minimum number of NOR gates.

(b) Does your implementation in part (a) contain any hazards? If so, find the best two-level NOR-NOR circuit that is free of all hazards. 

An M-N flip-flop works as follows:
If MN = 00, the next state is 0.
If MN = 01, the next state is the same as present state.
If MN = 10, the next state is the complement of the present state. If MN = 11, the next state is 1.

A) Q+ = NQ + MQ′

B) QQ+       MN

00      0X

01    1X

10    X0

11    X1 

C)MC = B, NC = A, MB = AC′, NB = C′, MA = C′, NA = B + C′

S1S0 = 00 hold, 01 shift right, 11 parallel load, 10 shift left.

Shift inputs DR and DL, Parallel inputs P3P2P1P0

CP M I3 I2 I1 I0

Q3Q2Q1Q0 S1S0

0000 01

1000 01

1100 01

0110 11

1101 10

1011 10

0111 01

0011 01

0001 01

XXXX XX

The equations are 

DR DL P3P2P1P0

1XXXXX

1XXXXX

0XXXXX

XX1101

X1XXXX

X1XXXX

0XXXXX

0XXXXX

0XXXXX

XXXXXX

DR = Q0'Q2', DL = 1, S1 = Q0'Q1 + Q0Q3, S0 = Q0'+Q3', P3P2P1P0 = 1101 

A basic lawn sprinkler system waters the lawn at 8am, once every 3 days. Its operation can be

modeled as a Moore-style finite state machine, where a clock period is one day, and a binary output W indicates whether the sprinkler is activated (W=1) or not (W=0) on that day. Show a transition diagram for this sprinkler control system.

An advanced sprinkler system has a rain sensor. The presence of rain during a particular day is indicated by the binary input R (with values 0/1 indicating No/Yes_rain). This sprinkler waters the lawn once every 3 days, assuming there has been no rain during previous 2 days. Show a transition diagram (Moore-style) for this advanced sprinkler system. 

Implement the transition diagram of a sprinkler system in part (b) using T flip-flops and external gates. Use straight binary state assignment.
Does your implementation have any unused states? If so, is your design self-starting? 

Consider a bus controller that receives requests on separate lines, r1, r2 and r3, from 3 devices

that want to use the bus. It has 3 separate outputs, g1, g2, g3, only one of which equals one, at any given time, indicating which device is granted control of the bus during that clock period. The lower numbered device has higher priority. So the bus controller has 4 states:
Idle ~ no device is using the bus gnt1 ~ device 1 is using the bus

gnt2 ~ device 2 is using the bus gnt3 ~ device 3 is using the bus.
Further, assume non-preemptive priority service, where once device j gets control of the bus (gnt_i =1), it retains control until it is no longer requesting the bus (i.e., until r_i=0). The controller must return to the Idle state for at least one clock cycle between different device allocations.
This bus controller can be implemented using Moore-style finite state machine, as discussed in lecture notes and reproduced below. 

(a) Show an algorithmic SM chart for this bus controller.
(b) Derive the next state equations and the output equations directly from your ASM chart (use straight binary state assignment).
(c) Suppose the bus controller is implemented using a ROM and D flip-flops. What is the smallest size ROM required? 

[image]

(b) Denote state variables AB and use the following state assignment: Idle~00, gnt1~01, gnt2~10, gnt3~11
Then:

g1 = A’B g2 = AB’ g3 = AB
A+ = A’B’r1’r2 + AB’r2 + A’B’r1’r2’r3 + AB r3 B+ = A’B’r1 + A’Br1 + A’B’r1’r2’r3 + AB r3

(c) We need to implement system with 3 inputs, 2 state variables (FFs) and 3 outputs. So we need ROM with 5 inputs and 5 outputs, of min size 32x5 bits.