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2) Explain why it is customary to measure etest parameters on a wafer at five points (five sets of etest structures) on a wafer. Specifically, state what would be lost with fewer measurements and what would be lost with more measurements. (3 points)
If a five-point sample is used for scribeline etest, the points would typically be chosen to spatially sample the wafer including the center, top, bottom, left, and right portions. This provides insight in case the problems are contained in only one of these regions. With fewer samples one would be forced to give up this level of spatial sampling. In addition, five points a reasonable statistical sample in order to determine a wafer-level average and standard deviation.

Sampling more points would increase the confidence in the results (spatially and statistically), but would add test time to the etest operation and therefore increase wafer cost.
3) In general, small package footprints (defined as the planar area of the package) are desirable. What are the limiting factors (in general) that prevent package footprint reduction for any given device? Mention 3 such factors, and briefly explain each.
(3 points)
Although an ideal package footprint would be limited only by the size of the die (i.e., the package footprint equals the die footprint), there are multiple practical issues to overcome in achieving this. A few of these concerns are listed:

• Strategies involving standardization of package footprints for a product family (to avoid the need for PC board relayout by end-users) are at odds with strategies of reducing package footprint with die-size reduction.
• The density of package signals increases with decreased package size, creating test and board-mount challenges. Leads/balls become smaller and closer together. Surface-mount is generally required. Customer handling becomes increasingly difficult.
• Flip-chip package technology offers high signal density within an area equal to the die size, but at increased complexity/cost due to required “bumps” that must be applied to bondpads prior to packaging.
• The ability of the package to dissipate heat generated by the die is reduced with smaller footprint, due to the reduced surface area available for heat convection or conduction to occur. Reducing package size tends to increase package theta-JA. The function of the package as a heat-sink is diminished with smaller footprint.
• For a wirebond package, as signals to the package increase in density there is greater possibility of cross-talk between adjacent bondwires. Also, if the increased density requires smaller wires, the bondwire resistances increase.
4) A typical VLSI product manufacturing flow includes several hours of burn-in. If, for example, six hours is good for the product, why wouldn’t seven hours be better?
The amount of time a product spends in burn-in is dependent on the characteristics of the latent defects being screened during the stress (their activation energies and voltage acceleration factors), as well as on the actual latent defect density and the quality goals of the VLSI manufacturer. If all of this is known, a Quality and Reliability engineer can use the Arrhenius equation to calculate the appropriate burn-in conditions and duration to achieve the desired level of outgoing quality.

Although additional burn-in beyond this optimal duration would further reduce outgoing infant mortality levels, it would come at a cost. Burn-in is an expensive operation, and the longer the burn-in duration the more equipment time is required. For this reason, burn-in duration is based on the “minimum but sufficient” requirement, based on the data and analysis mentioned above.
5) A manufacturer of VLSI products would like to save money by performing burn-in on devices without using burn-in ovens to elevate temperature. The idea is that the device self-heating that occurs during dynamic burn-in will produce a sufficiently high temperature to sufficiently accelerate latent defects to failure. Conditions:
o Nominal Vdd supply voltage of 3.3V. Burn-in voltage = Vdd+20%.
 Note: Assume constant current through the above Vdd range
o Nominal dynamic power consumption of 10W (at nominal Vdd voltage).
o Package theta-JA value of 5°C/watt.
o Ea=activation energy=0.7eV. C=voltage acceleration factor=0/volt.
a) Assume the burn-in chamber and the nominal customer-use temperature are both 30°C ambient and use the Arrhenius relationship to determine the acceleration factor associated with a 6-hour burn-in operation under these conditions. Comment on whether you think the manufacturer’s idea has merit. (4 points)
b) Repeat the calculation assuming the burn-in is performed in an oven set at 65°C
(2 points)
Answer (a):

The only difference between the conditions assumed for burn-in and for customer use in (a) is that the device is operated at a elevated voltage of Vdd+20% during burn-in, resulting in 20% higher power consumption (assuming constant current). Ambient temperature of 30°C is given for both conditions

Calculate junction temperature using equation Tj = Ta + theta-JA*power:

At nominal power of 10W … Tj = 30°C + 5°C/watt*10 watts = 80°C
At burn-in power of 12W … Tj = 30°C + 5°C/watt*12 watts = 90°C

Convert temperatures to Kelvin scale and use equation derived from Arrhenius Equation to determine thermal acceleration resulting from the slightly higher burn-in temperature. Note that no voltage acceleration occurs (voltage acceleration factor of 0 is given).

• AF (acceleration factor) = e([-Ea/k] [1/Tburn-in-1/Tuse])
• AF = e([-0.7eV/8.6e-5 eV/°K][1/363°K -1/353°K]) = 1.88
• Therefore, 6 hours of burn-in is equivalent to 11.3 hrs (1.88*6 hrs) of customer use. This method is not very effective.

Answer (b):

In the revised calculation, we assume a burn-in ambient temperature of 65°C.
At burn-in power of 12W … Tj = 65°C + 5°C/watt*12 watts = 125°C

• AF = e([-0.7eV/8.6e-5 eV/°K][1/398°K -1/353°K]) = 13.46
• The burn-in is enhanced greatly by the increased ambient temperature. Under this condition, 6 hours of burn-in is equivalent to 80.77 hrs (13.46*6 hrs) of customer use.

Note: In both of the above cases, we are assuming that the customer is doing nothing to cool the device in the application. If customer use temperatures are actually lower, acceleration factors for both scenarios (a) and (b) will be enhanced.
7) If a product datasheet quotes a maximum ambient operating temperature of 85C for a device, why might class testing be done at a temperature significantly higher than that, for example at 97C? (3 points)
Since the class test operation is kept as short as possible, self-heating may not have time to fully evolve the increased junction temperature expected under customer-use conditions. In order to simulate that increased temperature, the class test operation is deliberately run at an ambient temperature higher than the product datasheet permits. This temperature adder (12°C in this example) is calculated from the equation relating junction temperature to power consumption:
Tj = Ta + theta-JA*power.
8) Why do we need to test products in manufacturing if design simulation has already shown that they are functional and meet the required performance criteria over the specified voltage and temperature range? (3 points)
The purpose of manufacturing test is to identify devices that contain defective circuits, impacted by either point defects or by parametric problems. These problems are unavoidable in VLSI processing and if they go undetected in testing will be passed on to the end customer. The product design does not take into account these problems (with the exception of memory redundancy circuitry) and will not function under these varied and at times severely altered conditions.

Design validation testing of non-defective finished product is a standard procedure to check in silicon the behavior of the device with respect to the design models. This is typically done only once for any new design and is an engineering activity, not a manufacturing activity.
9) Explain briefly how the electronic test data derived from each of the operations below is used by engineers to monitor and improve product cost or quality. Briefly describe the type of data collected, and what kinds of manufacturing problems it may indicate.
a) E-Test (3 points)
b) Sort Test (3 points)
c) Class Test (3 points)
Answer (a):

Raw etest data is analog, measuring electrical parameters such as Vt, idsat, resistance, breakdown voltages, etc. on discrete structures. Control limits are established for these parameters such that if the product’s etest data falls above or below those limits the wafer is scrapped and root-cause understanding of the problem is pursued. At etest, most problems encountered relate to silicon process issues, and in particular are a strong indicator of parametric issues.

Answer (b):

Raw sort test data is in the form of pass/fail results, with failure information represented at the highest level by a “bin number” associated with the test that failed. Failure rates for the various bins (tests) are determined and are usually represented in the form of a pareto chart, ordering the tests according to their failure rates. This format is used to identify tests producing the highest yield loss. At sort test, most problems encountered relate to silicon process issues, and in particular are a strong indicator of point defect problems.

Answer (c):

Like sort test, raw class test data is in the form of pass/fail results, with failure information represented at the highest level by a “bin number” associated with the test that failed. Unlike sort test, units passing class test are also categorized. Passing unit results are classified into performance bins (e.g., bin1, bin2, bin3) reflecting how well they perform to AC datasheet parameters. The distribution of performance bins is referred to as “binsplit”, and is dependent on fab process targeting, design capability, and datasheet spec (test) limits. Failure rates for the various failing tests are determined and provide insight into a range of possible problems, including fab defects unscreened at sort, AC performance failure, assembly problems, and burn-in related failures (which reflect on product infant mortality levels).
10) Name the two primary reasons for designing a VLSI manufacturing flow to permit identification of manufacturing problems as early in the flow as possible. (3 points)
There are actually several possible answers (any two of these would be OK):

1. Early problem detection will allow earlier corrective action for problems
2. Early problem detection will facilitate containment of the material impacted by the problem. Suspected bad material can be sequestered. Suspected bad process steps can be shut down. Material suspected of being unreliable can be held in-line for further evaluation.
3. Early problem detection will provide more leadtime to the Product Planner to make adjustments to product shipment plans (schedules, customer commitments), minimizing disruption to the supply line and shipments
4. The closer a problem is found to the source, the greater the ability trace the problem to root-cause. Proximity to the operation that is the source of the problem, and to its engineers, improves problem-solving capability.
5. Discarding unviable devices as early in the flow as possible saves the additional cost of processing them through subsequent manufacturing steps
4) Calculate the number of finished, shippable units produced per week of a given product from a fab that starts 10,000 wafers per week of the product into the manufacturing line. Clearly show all intermediate results and all calculations to ensure credit! Assume the product and yield parameters listed below:
(6 points)

a) 10,000 wafers per week started into fab line
b) 900 whole (untested) die per wafer
c) Fab process yield of 93% (excluding etest)
d) 1% of all wafers etested are rejected due to parametric problems
e) Sort test defect-limited die yield of 80%
f) Assembly yield of 99%
g) Burn-in process yield of 99.9%
h) Class test yield of 97%
i) Mark and Pack yield of 99.9%
Wafer Yields = fab process yield * etest yield = 0.93*(1.00-0.01) = 0.9207
Die Yields = whole raw d/w * sort test yield = 900 d/w * 80% = 720 d/w
Unit Yields = assembly yield * burnin yield *class tests yield *M&P yield
= 0.99*0.999*0.97*0.999 = 0.9584
Total weekly wafers in = 10,000 wfrs
Total weekly units out = 10,000 wfrs * 0.9207 * 720 d/w * 0.9584 = 6,353,272
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