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| converts VHDL code to hardware structure |
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| How does concurrent statements execute? |
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| What does body of a process contain? |
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| Either a sensitivity list or a wait statement |
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| Process must not have what? |
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Definition
| Both sensitivity list and wait statement |
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| What is a sensitivity list? |
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Definition
| signals that are read in the process |
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| When is a process executed? |
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Definition
| When a signal in sensitivity list changes value |
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| What is an exception when a process has "if rising_edge"? |
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Definition
| process only need to include the clock signal |
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| Can concurrent assignment be translated to sequential statement? What are vice versa? |
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Definition
| All concurrent assignments can be translated to sequential statements, but not all sequential statements can be translated to concurrent statements |
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| Combinational process must have what? |
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Definition
| Must have a sensitivity list |
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| Combinational process must not have what? |
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Definition
| "wait" statements and "rising_edge" |
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| Clocked process must have what? |
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Definition
| "wait" or "if rising_edge" |
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Term
| What are the intuitions behind delta cycle simulation? |
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Definition
1. events appear to propagate through combinational circuit instantaneously
2. all of the gates appear to operate in parallel |
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| In delta cycle simulation, what are three states? |
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Definition
| suspended, postponed, active |
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Term
| In delta cycle simulation, what is suspended state? |
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Definition
| nothing to currently execute |
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Term
| In delta cycle simulation, how to go from suspended state to postponed state? |
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Definition
| change in sensitivity list or condition in "wait" statement hits |
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Term
| In delta cycle simulation, what is postponed state? |
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Definition
| wants to executed, but not currently active |
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| In delta cycle simulation, how to go from postponed state to active state? |
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Definition
| the simulation choose from the pool of postponed processes |
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| In delta cycle simulation, what is active state? |
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Definition
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| In delta cycle simulation, how to go from active state to suspended state? |
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Definition
| hits "wait" statement or sensitivity list |
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Term
| What are two features delta cycle simulation doesn't support? |
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Definition
1. delayed assignments
2. resolution, which is multiple processes write to same signal |
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| In delta cycle simulation, in n-threaded execution, how many processes are active? |
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Definition
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| In delta cycle simulation, what is a simulation step? |
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Definition
| executing one sequential assignment or process mode change |
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| In delta cycle simulation, what is a simulation cycle? |
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Definition
| the operations that occur in one iteration of the simulation algorithm |
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Term
| In delta cycle simulation, what is a delta cycle? |
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Definition
1. a simulation cycle that does not advance simulation.
2. a artificial unit of time that's infinitely small |
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| In delta cycle simulation, what is a simulation round? |
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Definition
| a sequence of simulation cycles that all have the same simulation time |
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Term
| What is a good design for creating test-bench with respect to clk and signals? |
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Definition
| change in signals shouldn't happen at the same time as clk edge |
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| What RTL simulation cannot simulate? |
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Definition
| cannot simulate combinational loops |
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Term
| Why are flops free in FPGAs? |
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Definition
| area consumed by a design is usually determined by the amount of combinational circuit, not by the number of flops |
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| How much percent of area should be used in a chip? |
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Definition
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| Should different clock edges be used? |
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Definition
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| Compare Moore machines with Mealy machines |
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Definition
1. State: Moore machines depend only on the state but Mealy machines depend both on state and the inputs
2. Combinational path: Moore machines doesn't support calculations but Mealy machines supports calculations |
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| In dataflow diagram, how to know how many inputs? |
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Definition
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| In dataflow diagram, what are clock cycle boundaries? |
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Definition
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| In dataflow diagram, how to know how many flops should be used? |
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Definition
| signals crossing clock boundary |
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| In dataflow diagram, how to know how many outputs? |
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Definition
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| In dataflow diagram, how to know what's the latency? |
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Definition
| number of clock cycle boundaries |
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| In dataflow diagram, how to know that's the min clock period? |
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Definition
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| In pipe line, what's fully pipelined? |
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Definition
| throughput is one parcel per clock cycle |
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| In pipe line, what's partially pipelined? |
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Definition
| throughput is less than one parcel per clock cycle |
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| In pipe line, what's superscalar? |
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Definition
| throughput is more than one parcel per clock cycle |
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| In pipe line, what's depth? |
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Definition
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| In pipe line, what's latency? |
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Definition
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| In pipe line, what's throughput? |
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Definition
| number of parcels consumed per clock cycle |
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| In pipe line, what's bubble? |
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Definition
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| In pipe line, how to know whether the output of the pipeline is a bubble or is valid data? |
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Definition
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Term
| write a picture for read after write |
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Definition
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| Write a picture for write after write |
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Definition
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| write a picture for write after read |
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