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Definition
| Rewriting a JMP instruction at the end of one program's interrupt handler to jump to the old handler |
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| Allows relatively slow devices to get attention from a processor in a timely manner without polling. |
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Term
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| Two branches: Shared irq and interrupt. The shared irq allows the interrupt vector to be shared by other handlers, but only if all of the handlers agree to share. The shared interrupt flag keeps all interrupts masked on the processor throughout the handler's execution, and should only be used for short handlers. |
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| Keeps track of info pertaining to interrupt vectors in this array. |
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| Removing interrupt handler |
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| Links the interface used by the hardware to the calling convention used when compiling do_IRQ |
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| Executed by the do_IRQ function. Set to stack. |
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Definition
| a data structure used to wrap a single handler function used as a soft interrupt handler. |
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| fist checks whether or not an interrupt of any type, either hard or soft, is already being executed by the processor. If so, function terminates. |
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Definition
| you can assign values to macros and increment them. |
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Term
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Definition
| Repeatedly attempts to obtain a lock by atomically reading a bit from memory and replacing that bit with a 0 (using either an instruction with a LOCK prefix or a special atomic instruction). |
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Definition
| The insertion of a level of indirection between the memory address space seen by a program and the address space of the actual memory in the system. |
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Definition
| Addresses seen by the program |
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Term
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Definition
| same as virtual addresses |
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Term
| Memory management unit (MMU) |
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Definition
| The hardware that translates virtual addresses to physical addresses. |
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Definition
| A level of virtual memory that prevents the memory used by the second program to be used by the first. |
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Definition
| Allows libraries to share without modifying code through library code placement in physical memory and mapping to two or more programs. |
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| Occurs when a system without virtual memory attempts to run more than one program at a time. |
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Definition
| Changing the absolute addresses used by each program back to their original location. |
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Term
| Current privilege level (CPL) |
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Definition
| Part of the processor state. Holds the present marker of privilege |
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Term
| request privilege level (RPL) |
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Definition
| In charge of accesses made to code or data, and allows code executing on behalf of less privileged code to have the hardware check to the necessary privileges for certainty rather than making all checks in software. |
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Term
| descriptor privilege level (DPL) |
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Definition
| Associated with each memory location accessed. If either the CPL or RPL is greater than the DPL, the processor generates an exception, preventing illegal access. |
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Term
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Definition
| A contiguous portion of an address space, such as the 32-bit space of physical addresses. |
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Term
| Global Descriptor Table (GDT) |
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Definition
| Used by any program, this table is held in a 48-bit register with a 16-bit limit. |
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Term
| Local Descriptor Table (LDT) |
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Definition
| Used within a program. Similar setup to the GDT. |
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Term
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Definition
| Used to cache the values stored in the GDT or LDT. These are bits that are not directly accessible to the ISA. |
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Definition
| Intended to hold information pertaining to an individual program. |
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Term
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Definition
| When a page exists but it is not in physical memory, just present on a disk. |
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Definition
| Data kept on this disk comes from data that is in use, but had to be moved out of memory to make room for more data or another program. |
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Definition
| An encoding used for the page table, and it holds a single page to be mapped to physical memory. |
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Definition
| An array of page table entries that stores the mapping from virtual to physical memory of a disk. |
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Term
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Definition
| Organized set of page tables, with each page table represented by a page directory entry (PDE), which can indicate that the page table does not exist, or that it's not in physical memory. |
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Term
| Page Directory Base Register (PDBR) |
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Definition
| Aka Control Register 3 (CR3), this register holds the physical address of the page directory. |
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Term
| Translation lookaside buffers (TLBs) |
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Definition
| Additional hardware to cache the results of a translation. Maps a 20-bit virtual address for a program into a 20-bit physical address. |
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Definition
| When the access (load or store) needs a translation, even though no TLB holds the necessary mapping for an address. Control of TLB then moves to hardware or OS. |
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| Discarded; usually referring to translations. Occurs when the value of the PDBR is changed |
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Term
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Definition
| a component that transparently stores data so that future requests for that data can be served faster |
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