Term
| What is computer architecture? |
|
Definition
| science and art of selecting and interconnecting hardware components to create computer that meet functional, performance, and cost requirements |
|
|
Term
| What are several goals for computer architecture? |
|
Definition
1. functional
2. reliable
3. performance
4. low cost
5. low power/energy |
|
|
Term
| Why is it important to build a computer that fits the application domain? |
|
Definition
| Difference application domain might have different requirements |
|
|
Term
| What are advantage of hardware? what are disadvantage of hardware? |
|
Definition
ADV: parallelism, faster
DIS: less flexible |
|
|
Term
|
Definition
| instruction set architecture |
|
|
Term
| What is instruction level parallelism? |
|
Definition
| many operations performed simultaneously |
|
|
Term
| give an example of instruction level parallelism |
|
Definition
|
|
Term
| what is data level parallelism? |
|
Definition
| distributing data across different computing nodes (computing in parallel) |
|
|
Term
| give an example of data level parallelism |
|
Definition
|
|
Term
| what is thread level parallelism |
|
Definition
|
|
Term
| give an example of thread level parallelism |
|
Definition
|
|
Term
| what is the difference of data level parallelism and thread level parallelism? |
|
Definition
|
|
Term
| What are two strategies RISC processors use? |
|
Definition
| instruction level parallelism and use of caches |
|
|
Term
| What are three important criteria in server? |
|
Definition
1. availability
2. scalability
3. efficient throughput |
|
|
Term
| what are two criteria in warehouse scale computers? |
|
Definition
1. price-performance
2. power |
|
|
Term
| What is task level parallelism? |
|
Definition
| execute tasks in parallel |
|
|
Term
| what's difference between thread level parallelism and task level parallelism? |
|
Definition
|
|
Term
| which parallelism can be applied to single instruction stream, single data stream? |
|
Definition
| instruction level parallelism |
|
|
Term
| give an example of single instruction stream, single data stream |
|
Definition
|
|
Term
| which parallelism can be applied to single instruction stream, multiple data stream? |
|
Definition
|
|
Term
| give an example of single instruction stream, multiple data stream |
|
Definition
|
|
Term
| which parallelism can be applied to multiple instruction stream, multiple data stream? |
|
Definition
| task level parallelism, request level parallelism |
|
|
Term
| give an example of multiple instruction stream, multiple data stream |
|
Definition
|
|
Term
| give a equation to calculate dynamic energy for 0->1 or 1->0 transition |
|
Definition
|
|
Term
| give a equation to calculate dynamic power |
|
Definition
| 1/2 * c * v^2 * frequency switched |
|
|
Term
| give a equation to calculate frequency switched |
|
Definition
|
|
Term
| reducing in voltage will cause frequency switched to do what? |
|
Definition
| reducing the frequency, since it takes longer time for capacitors to charge and discharge now |
|
|
Term
| what is dynamic voltage-frequency scaling |
|
Definition
| reduce voltage when not using the computer |
|
|
Term
| what's the difference between latency and throughput? |
|
Definition
latency: time
throughput: work/time |
|
|
Term
| what are two reasons MIPS sucks? |
|
Definition
1. work per instruction is different (ADD might have 2 instructions but SUB might have 1 instructions)
2. ISAs are not the same(in intel, ADD might be 3 instructions but AMD, ADD might be 1 instructions) |
|
|
Term
| what is the equation for program run time? |
|
Definition
|
|
Term
| derive latency and through put from program run time equation |
|
Definition
| remove inst/prog from program run time equation -> becomes latency |
|
|
Term
|
Definition
performance optimization is limited by fraction which cannot be optimized.
This means need to decrease fraction which cannot be optimized using principal of locality |
|
|
Term
| what is the most important technique used to improve performance? |
|
Definition
|
|
Term
| what is disadvantage of over-using pipelining? |
|
Definition
1. frequency will be limited by registers
2. if too much stages, then too much overhead for branching(we use a lot of branching in our codes!) |
|
|
Term
| why increasing transistors will increase CPI? |
|
Definition
| increase transistors -> area increase -> more CPI |
|
|
Term
| How to measure dynamic instruction? |
|
Definition
|
|
Term
| How does CPI break down work? |
|
Definition
|
|
Term
| How to understand frequency switched? |
|
Definition
|
|
