- air flow management to reduce cooling

- liquid cooling

- white walls/ceilings...

- cooler climats

- cloud computing

- match vdd to performance needs

- reduce vdd for circuits that are not timing critical

- but, how many levels?

1. Reduce vdd

2. circuit is slower since transistors hardly turned on when Vdd approached VT (takes time to chard cap.)

3. Need to reduce VT

4. leakage increases (exp. with lower VT)

5. Pstatic > saved Psw

What is the big/little principle?

Two processors: one big (fast) one slow (energy efficient)

- identical ISA

- threads can migrate

- Number of active cores can vary

- Either big or little, (not both)

Name two "new" transistor techniques

FinFET

SD-FOI

Descibe FD-SOI

Transistor channel fully deplated of dopants ->

drain induced parasitic effects are removed ->

allowing lower VT (small or no leakage)

possible to dynamically VT with body biasing (not possible with FinFET).

Texe = IC * CPI * TC

IC  - # instr.

TC - Clock cycle time

CPI - clock cycles per instr.

Texe = Texe(without E)*((1-F) + F/S)

Speedup = 1/((1-F) + F/S)

Functional simulation - mimic HW behaviour

(user vs full system?)

Cycle level simulation - impact of structure characteristics on exec time and energy

simple salar, Wattch

(much slower than functional simulation)

(stuctures - Branch pred, ROB, BTB, BPB)

Trace driven simulation - generate exec. trace that drives sumulation

Execution driven simulation - generate the trace "on-the-fly"

Direct exection - Exectute parts of a program on a host and then dispatch to the simulator for detailed modeling

- Micro arch. trade-offs

- Compiler optimization

- Hardware optimization

What can you get from power modeling?

(power modeling methology)

- Estimate capacitance of different structures

(array structures, ROB, combination logic)

Appliction Specific Instruction set Processor

- add/remove instructions (eg. FP instr.)

- More energy than fixed ISA processors

- More flexible than dedicated accelerators

Application Specific Standard Product

- off the shelf

- microprocessor / microcontroller

- limited performance

- easy to use

- complex implementation and verification

- multiple Vdds

- Synchronization between different blocks

- Multi-domain clocks

Describe pipelining

- Many unneccessart accesses to the reg. file.

- many unneccessary accesses to the pipeline registers

- forwarding and hazard logic unneccessarily checked

- repeated calculation of unchanged values

• Modified Storage Cell (MSC)
• Precise Read Control (PRC)
• Latch clock gating (LCG)
• Bypass Skip
• Bypass R0
• Split bitline
• Read caching

slipt register file into two part

- one small part with registers that are frequently used

- one larger part with registers that are less frequently used

blitlines in the larger set are only precharged when it needs to be accessed

- outputs are forwareded back to the input and never leave the ALU

-  Pro: avoid access and updates to bypass latches and register file

- Con: added complexity

A cache system is coherent if all processors, at any time, have a consistent view of the last globally written value to each location

- snoopy cache protocol

- Modified Shared Invalid (MSI) protocol (copy-back)

invalidate other cached copies

-two states invalid/valid

three states: modified, shared, invalid

writes only cause bus traffic when a block is in S state

name two snoopy cache access energy reduction techniques.

Jetty - filter associated with each private cach that establish whether a lookup is needed

(much smaller -> less energy / access)

(Exclude, Include, Hybrid Jetty)

Serial snooping - do tag lookup serially instead of in parallel. once a hit is detected further tag lookup are not needed.

Wider issue favors:

- favor serial and parallel applictions with alot of ILP

(for parallel - since communication can go through private caches)

More cores favor:

- favor parallel applications with limited ILP and communication

(more cores -> more efficient arch but more energy spent in memory)

try to get the processor to run a at a lower speed

higher speed -> more power consumed

• packaging and cooling
• operation cost
• perofrmance
• reliability
• battery life
• device lifetime
• ergonomics

• accuracy
• cost
• resolution
• level sensitivity
• overhead

external av power meter

between wall and psu (power supply unit)

 pros: easy to use, low-cost, does not affect measured unit

cons: single measurement for whole system, accuracy affected by PSU, low sampling freq.

- measure between psu and motherboard

- require custom hw

- need to capture analog values

pros: protable across all ATX mbs, high sensitivity and sampling rate

cons: high cost, more impact on system thea wall socket

Pros: accurate absolute values, high sensitivity

cons: have to solder on BM

- power meter by manufacturer

- accessible to programmers

- Intels RAPL

pros: no additional cost, easily accessible,

cons: estimations instead of measurement, lower res than some other methods, black box

why is not DRAM the future?

- poor technological stability

- bitline parasitic cap. making reliable sensing a challange

Phas change memory (PCM)

Magnetic RAM (MRAM)

Data stored in form of resistance. (with increased delay much less energy can be consumed than DRAM)

pros: denser than DRAM, refresh needed less often,

can scale further then DRAM

cons: slower than DRAM (R and WR),

more energy used (R and WR)

limited lifetime

gradually shifting values

- Store content of accessed rows

- importan for memories

--> slower than bus -> need to buffer

--> DRAM destructive reads

--> PCM writes costly

hit latency same for DRAM & PCM

RB miss large for PCM, small for DRAM

- magnetism used to store bit data

- "holy grail" of battery life

- use magnetic fields (left/right) to detect bit values

pros: no refresh needed,

non-volatile, infinite endurance, high speed, low cost

MRAM faster

MRAM non-volatile

MRAM no represh needed

MRAM better low-power possibilites

SAME

endurance (unlimited)

cell size (small)

name two new techniques for DRAM

MEMScale

RowClone

- active low-power modes (idle ranks)

- collaboration between HW and SW

- two techniques:

--> DVFS (for MC)

--> DFS (for memory channels)

will reduce the nubmer of bytes fetched from the memory system (can reduce accesses and misses).

Can reduce the number of ROM chips in an Embedded product

traditional compiler optimizaion techniques usually provide benefits for execution time, code size, and/or energy usage.

some compiler optimization techniques make trade-offs -> can increase the code size

- cross jumping

- code hoisting

- overlapping relocate code portions

- dual-width instruction set

- mixed-width instruction set

-echo instruction

- hardware dictionary compression

- instruction register file

describe dual-width instruction set

- can switch beteween two distince instruction sets

- frequently executed code use the large (high perf.) ISA

- less frequently executed code use a small (efficient code size) ISA

ex ARM/Thumb, MIPS32/MIPS16

can fetch 2 Thumb instr. in one cycle

thumb instr. need to be converted to ARM instr. (decompressed)

describe echo intrsuction

- Echo instr. is a lightweight function call

- execute a special set of instruction at a target location and returns (no need to execute return statement)

- seq. echo instr. - include # of instr. to execute

- bitmask echo instr. - include a bitmask to indicate which instructions to execute

- dictionary of common seq. of instr. is loaded fora given application.

- Variable length codewords are used to repr. the most freq. occuring seq. of instr.

Dynamic Instruction Sream Editing

- Use paramerterized dictionary compression

- Unused opcodes are used to specify that a dictionaty entry is tobe accessed.

- fast access

- multiple accesses at the samt time

 - accesses require little power

- references take little space

name three compiler optimizations that can be used to improve instruction packing

- instruction slection: Can replace instructions

- Register Re-assignment: some instructions only differ by the register  they reference

- Instruction scheduling: instr. can be scheduled to aviod constraints on packing instr.

Describe drowsy registers

- place inactive lines in a low-power mode

- more efficeient with partitioned caches

Simple policy: after N cycles sleep all lines

No Access policy: if not accessed in N cycles, sleep

Better policy: keep k last accesses lines awake, simpler than clock, lower hw cost and leakage

add small L1 cache for stack/global data

works well with: small footprints and well defined locality characterisitics (X)

Use small caches if (X) is fulfilled else place "HOT" data in the small caches

what is adaptable memory systems?

Problem statemet: widening memory gap, cache might fail on applixations with poor locality

Use addaptable MMC (main memory controllers)

(remap addresses in the MMC)

Benefit: better bus, cache, and TLB peformance