Initial Blocks

Delays 

What dataflow operators are not supported in synthesis?

Which ones are modified? 

Unsupported 

**

/

% 

Modified 

=== becomes ==

!== becomes != 

When you need priority encoded logic

Need multiple conditions tested

Speed is a priority 

Creates balanced logic

Tests common condition

Useful for complex decoders 

What's wrong with this module?

 module prio(q, a, b);

    output q;

    reg q;

    input [2:0] a;

    input b;

    always @(a) begin

        if (a[2])        q = b;

        else if (a[1]) q = ~b;

        else if (a[0]) q = 0;

    end

endmodule

Creates a latch - no else statement for if sequence. Either need to add an else, or make a default assignment.

Sensitivity list incomplete, needs b added to it 

What's wrong with this code?

module prio3(q, a, b);

    output q;

    reg q;

    input [1:0] a;

    input b;

    always @(a, b) begin

        case(a)

            1: q = b;

            2: q = ~b;

        endcase

    end

endmodule 

How do these two blocks synthesize?

always @(posedge clk)

    //code

versus

always @(enable)

    if (enable)

        //code

Don't mix flip-flops and latches

Prefer flip-flops to latches unless you have a specific reason for using one over the other. 

Flipflops require a larger are and more power

Clock period is constant for all flipflops unlike latches

Clock design for flipflops is easier and fully automated unlike latches where it is complex. 

How would you add an asynchronous low reset to this block? Synchronous?

always @(posedge clk) begin

    q <= d;

end

For asynchronous in the sensitivity list add "or negedge rst"

For either, replace the inside of the always block with

if (!rst)

    q <= 0;

else

    q <= d;

Spartan Primitive Library Elements:

FD 

FDC

FDR

FDP

FDE

RAMB16Sn 

FD: D Flip flop 

FDC : D Flip flop asynchronous clear

FDR : D Flip flop synchronous reset 

FDP : D Flip flop asynchronous preset

FDE : D Flip flop synchronous enable 

RAMB16Sn : block RAM where n selects the config

What's wrong with this code?

module dffrst(q, clk, rst, d);

    output q;

    req q;

    input clk, rst, d;

    always @(posedge clk or negedge rst) begin

        if (rst)

            q <= 0;

        else

            q <= d;

    end

endmodule 

What's wrong with this code?

module dffrst(q, clk, rst, set, d);

    output q;

    req q;

    input clk, rst, d, set;

    always @(posedge clk or set) begin

        if (set)         q <= 1;

        else if (rst)   q <= 0;

        else             q <= d;

    end

endmodule

For a dataflow model:

assign q = a + b * c; 

What must each of the variables (a, b, c, q) be defined as? 

q must be a wire

a, b and c can either be wires or regs 

For this code, what must each of the variables (a, b, c, q) be defined as?

always @(a or b or c) begin

    if (a > 2)

        q = a + b * c;

    else

        q = a - b * c;

end 

q must be a register

a, b and c can be either wires or regs

CLBs

IOBs

Block RAM

Multiplier 

DCM 

A piece of a CLB - 4 per CLB. Each slice can work as logic (gates + flipflop), distributed RAM, or a shift register.

Each slice has 2 LUTs, 2 flipflops, MUXes and Carry-logic 

Left is called SliceM and it can do logic, distributed RAM or shift register.

Right is called SliceL, it can only do logic. 

Act as either a logic function of up to 4 inputs, 16 bit ram, or 16 bit shift register.

4 bit input, 1 bit output.

They are found in Logic Slices, 2 per slice

Set of Inputs and Outputs

Set of States

Initial State (reset function)

State Transitions 

Use parameter to define state codes:

parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10 

Reset and update in same block.

Output will always have a register 

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Reset and update still in same block.

Output can be combinational. 

[image]

Reset and update in different blocks.

Output can be combinational.

[image]

Selects one bit for each state - each state transition flips only two bits.

Good for FPGA with lots of flip-flops, but not so efficient with a large number of states or state transitions. 

User Defined and Tool Defined.

User defined, use 'pragma' or 'synthesis constant':

(* fsm_encoding = user *) 

For the following FSM block, how would you assign a default state of s0?

always @(state or i) begin

    case (state)

        s0: if (i == 1'b0)

                   next_state = s1;

             else

                   next_state = s0;

        s1: ..

        endcase

end 

Add:

next_state = s0;

before the case statement. 

An FSM that will convert each invalid state automatically to a recovery state (usually the reset state)

Used when proper, precisely defined operation is more important than cost (area, performance) 

Synthesizing for BRAM for next-state logic and state register

Synthesizing as LUT-based FSM (default) 

Inference defines elements that may or may not be in a primitive library, and adds them if necessary.

Instantiation uses primitive library elements (e.g. FD) specific to the tools you're using.

Inference provides portable code that can compile on multiple targets, simulate with a generic simulator and provides maximal freedom to synthesis tools.

Instantiation gives designer maximal control over the synthesis process at the cost of nonportable code, assumption of a specific target, and use of a specific library. 

A decoder that takes a write address and connects to a register enables based on the decoded address. Registers are load-enable, edge triggered, and each one is connected to the write data.

[image]

2 decoders to enable a reg based on a decoded addr. 2 datas connected to the regs by a multiplexer. One write port has priority so that if both ports are accessed, the higher priority one determines the reg selection and which data is written.

[image]

SRAM (6 transistors/bit)

DRAM (1 transistor/bit) 

Row and Column Decoders used to access specific memory cells. Wordsize is equivalent to # of columns. # of words is equivalent to # of rows.

[image]

One transistor/capacitor per bit. Multiplexed address bus with Row and Col address selects.

Leakage current causes capacitors to discharge in a few ms, so DRAM memory needs to be continuously rewritten or 'refreshed'

Data is always read/written an entire row at a time. 

Write First: write occurs before read

Read First: read occurs before write

No Change: data-output port isn't changed 

How would you change this code for write first mode? read first mode?

input we; // write_enable

input [15:0] di; //data in 

reg [15:0] RAM [63:0]; //16-bit, 64 locations

reg [15:0] do; //data out 

always @(posedge clk)  begin

    if (en) begin

        if (we)

           **code**

    ...

    end

end 

Read First:

if (en)  begin

    if (we)

        RAM[addr]<=di;

    do <= RAM[addr];

end

Write First:

if (en) begin

    if (we)

        RAM[addr]<=di;

    do <= di;

end 

What's wrong with this code?

input [5:0] addr;

input [15:0] di;             //data in

output [15:0] do;          //data out

reg [15:0] RAM [127:0]; //16-bit, 128 locations

reg [15:0] do;

always @(posedge clk)  begin

    if (en) begin

        if (we)

            RAM[addr] <= di;

        do <= di;

    end

end 

In FPGA, what specifies the initial contents of BRAM?

How can you initialize BRAM contents? 

The bitstream

 To initialize:

initial

    for (i=0; i<64; i++)

        RAM[i]=i;

or:

$readmemh("hex.data", RAM, 0, 63)

A measure of performance of a design. Defined as Slices * clock cycles e.g.

400 slices, 20 cycles = 8000 Slices.cycles 

Expresses the potential amount of resource sharing in a digital design.

It is the amount of clock cycles available per data item.

HSF = fclk / max(fin,fout) 

Performance = 1 / Throughput or 1 / Latency

Delay = 1 / Performance 

By either reducing the Cycle Count or the Clock Period.

Delay = Cycle Count * Clock Period 

T_clk,min = T_clk->Q + T_Logic + T_Routing + T_Setup

 T_Logic and T_Routing can be reduced by the designer.

Margin between the actual clock period and the minimal clock period.

[image]

Parallel Computations

Pipelining

Retiming 

How would you divide this structure into a 3 stage pipeline? What would be the resulting T_clk,min, Latency, and Throughput be?

[image]

Delay from input to register

Delay from register to register

Delay from register to output 

If there are M inputs and N outputs, then there are

M*N possible paths. 

Tasks... 

Can contain event control (@, #, wait)

May execute in non-zero simulation time 

Can have 0 or more arguments of type in, out or inout

Functions... 

Cannot contain event control

Must execute in zero simulation time

Must have at least one input argument

Must have a single output argument