Term
| Design a 4-bit register with 2 control inputs s l and sO; 4 data inputs I3, I2, Il. and IO; and 4 data outputs Q3, Q2, Ql, and QO. When slsO=OO. the register maintains its value. When slsO=O l , the register loads I3 ... IO. When slsO=l O, the register clears itself to 0000. When slsO=ll, the register complements itself, so for example, 0000 would become 1111, and 1010 would become 0101. (Component design problem.) |
|
Definition
|
|
Term
Repeat the previous problem (see #1), but when sl sO=ll, the register reverses its bits, so 1110
would become 0111, and 1010 would become 0101. (Component design problem.) |
|
Definition
|
|
Term
Design an 8-bit register with 2 control inputs s l and so, 8 data inputs 17 ... IO, and 8 data
outputs Q7 ... QO. S1 S0=00 means maintain the present value, S l SO=Ol means load, and
slsO=l O means clear. slsO=l l means to swap d1e high nibble with the low nibble (a
nibble is 4 bits) . so 11110000 would become 00001111, and 11000101 would become
01011100. (Component design problem.) |
|
Definition
|
|
Term
|
Definition
|
|
Term
|
Definition
|
|
Term
Assmni11g all gates have a delay of 1 ns , compute me longest time required to add two
numbers using an 8-bit carry-ripple adder. |
|
Definition
| You will have a 3ns delay for the full adder because the full adder goes through 3 levels of gates. 1ns for the half adder, so we have 1 + (3*7) = 22. |
|
|
Term
| Design a 10-bit carry-ripple adder using 4-bit carry-ripple adders. (Component use problem.) |
|
Definition
|
|
Term
| Design a digital thermometer system that can compensate for errors in the temperature sensing device's output T, which is an 8-bit input to the system. The compensation amount can be positive only and comes to the system as a 3-bit binary number c, b , and a (a is tl1e least significant bit). which come from a 3-pin DIP switch. The system should output d1e compensated temperature on an 8-bit output U. |
|
Definition
|
|
Term
Trace through the execution of the 4-bit magnitude comparator shown in Figure 4.43 when
a=IS and b=l2. Be sure to show how the comparisons propagate thought the individual
comparators. |
|
Definition
|
|
Term
Design a system tbat determines if three 4-bit numbers are equal, by cmmecting 4-bit magnitude
comparators together and using additional component~ if necessary. |
|
Definition
|
|
Term
Design a circuit that outputs 1 if the circuit's 8-bit input eq uals 99:
(a) using an equality comparator,
(b) using gates only. |
|
Definition
|
|
Term
Use magnitude comparators and logic to design a circuit d1at computes the minimum of three
8-bit munbers. (Component use problem.) |
|
Definition
|
|
Term
Design an 8-bit shifter that shifts its inputs two bits to the right (shifting in Os) when the
shifter's shift control input is 1. (Compo11e11t design problem.) |
|
Definition
|
|
Term
Design a circuit whose 16-bit output is nine times its 16-bit input D representing an unsigned
binary number. ignore overflow issues. (Co111po11ent use problem.) |
|
Definition
|
|
Term
Design a 4-bit up-counter that has two control inputs: cnt enables counting up. while
clear synchronous ly resets the counter to all Os using a parallel load register as a building block, |
|
Definition
|
|
Term
| Design a circuit for a 4-bit dccremcnter. (Co111po11e11t desig11 problem.) |
|
Definition
|
|
Term
| a) What is the formula for the count range for an up-counter? |
|
Definition
|
|
Term
| Layers of abstraction diagram with ISA |
|
Definition
|
|
Term
Rewrite in assembly:
int t = x+y; |
|
Definition
addl 8(%ebp),%eax
(%ebp and %esp have special use cases) |
|
|
Term
| Memory address computation |
|
Definition
|
|
Term
| Draw a D latch internal circuit using logic gates |
|
Definition
|
|
Term
| Draw a D flip-flop using two D latches in a master-servant arrangement. |
|
Definition
|
|
Term
| SR Latch - Feature and Problem |
|
Definition
|
|
Term
| Level Sensitive SR Latch - Feature and Problem |
|
Definition
|
|
Term
| D Flip Flop - Feature and Problem |
|
Definition
|
|
Term
| D latch - Feature and Problem |
|
Definition
|
|
Term
Boolean Algebra Terminology: F(a,b,c) = a’bc + abc’ + ab + c
What are the variables? |
|
Definition
| Three variables: a, b, and c |
|
|
Term
Boolean Algebra Terminology: F(a,b,c) = a’bc + abc’ + ab + c
What are the literals? |
|
Definition
– Appearance of a variable, in true or complemented form
– Nine literals: a’, b, c, a, b, c’, a, b, and c |
|
|
Term
Boolean Algebra Terminology: F(a,b,c) = a’bc + abc’ + ab + c
What are the product terms? |
|
Definition
– Product of literals
– Four product terms: a’bc, abc’, ab, c |
|
|
Term
Boolean Algebra Terminology: F(a,b,c) = a’bc + abc’ + ab + c
Sum of products? |
|
Definition
– Equation written as OR of product terms only
– Above equation is in sum-of-products form. “F = (a+b)c + d” is not. |
|
|
Term
Boolean Algebra: Additional Properties
Null elements |
|
Definition
|
|
Term
Boolean Algebra: Additional Properties
Idempotent Law |
|
Definition
|
|
Term
Boolean Algebra: Additional Properties
Involution Law |
|
Definition
|
|
Term
Boolean Algebra: Additional Properties
DeMorgan’s Law |
|
Definition
– (a + b)’ = a’b’
– (ab)’ = a’ + b’
– Very useful! |
|
|
Term
1. Canonical Form Sum of Minterms Defintion
2. Determine if F(a,b)=ab+a’ is same function as F(a,b)=a’b’+a’b+ab, by
converting first equation to canonical form (second already in canonical
form) |
|
Definition
1. Truth tables too big for numerous inputs; use standard form of equation instead (known as canonical form)
- Minterm: product term with every function literal appearing exactly once, in true or complemented form
2. F = ab+a’ (already sum of products)
F = ab + a’(b+b’) (expanding term)
F = ab + a’b + a’b’ (SAME -- same three terms as other equation) |
|
|
Term
|
Definition
- n-input has 2^n outputs
- outputs 1 if the input exists |
|
|
Term
|
Definition
| - copies the value from the input if there is an input |
|
|
Term
| Create truth table and circuit for 8x1 multiplexor |
|
Definition
|
|
Term
| Truth table and circuit for 3x8 decoder |
|
Definition
|
|
Term
| Logical steps: Decimal to Two's complement |
|
Definition
|
|
Term
| Logical steps: Two's Complement to Decimal |
|
Definition
|
|
