Combinational elements - outputs depend on inputs

- boolean equation

- has latency

   - no internal storage

   - E.G. ALU

Sequential or State elements - have state, i.e. memory (while power is present)

 - need to be intialized (on applying power)

 - inputs

- at least one level input

- a clock

 - output depends on state and input(s)

Idea:

1. Shareable functional units (FU)

- single memory

- single ALU (instead of 3)

- register

2. Break instruction into multiple cycles

Some Attributes:

1. Can share FUs as long as in a different cycle

2. Extra registers

- have to save results to be used during the next clock

- need

- ALUOut

- A, B (source registers)

- Memory data register

- Instruction Register

- not visible to ISA

3. Need extra multiplexers

- to select register for multiple purposes

1. Instruction Fetch (IF)

- fetch instruction from memory

2. instruction decode/register fetch (ID)

- read registers while decoding the instruction.  the format of 

  MIPS instructions allows reading and decoding to occur sim.

3. execution/effective address (EX)

- execute the operation or calculate an address

4. memory access (MEM)

- access an operand in data memory

5. write-back (WB)

- write the result into a register

instructions be the same length

to have few instruction formats

memory is accessed only in loads & stores

operands must be aligned in memory

structural (due to limited hardware resource)

data (due to data depend. between instruct.)

control (due to branching)

stall on branch

branch prediction

delayed branch

temporal locality - if a memory location is referenced, it will tend to be referenced again very soon

spatial locality - if a memory location is referenced, it is likely that a nearby lcoation will be referenced soon

SRAM                .5-2.5 ns $2k-$5k

DRAM  50-70 ns $20-$75

Magnetic disk 5mil-20mil ns $.20-$2

block/line

hit, miss

hit rate/ ratio

hit time

miss rate/ ratio

miss penalty

hit time - time to establish if hit or miss, and then to access faster mem.

miss penalty - time to retrieve block, and to replace it in faster mem.

16KB = 4K words or 2¹² words

a block size of 4 words (2²)

so (2¹⁰) blocks

each block has 4x32 or 128 bits plus tag bit (32-10-2-2) and a valid bit.

so the total cache size is = 

2¹⁰x(128+(32-10-2-2)+1) = 2¹⁰x147 = 147Kits

1200/16 = 75

75%64 = 11

11

1. send the address to the mem

2. instruct main mem to perform a read and wait for the mem to complete its access

3. write the cache entry, putting the data from mem in the data portion of the entry, writing the upper bits of the address (from the ALU) into the tag field, and turning the valid bit on

4. restart the instruction execution at the first step, which will refetch the instruction, this time finding it in the cache.

write-through- writes to cache and mem, caches is never inconsistent, large mem latency (uses write buffer)

write-back- writes only to cache, better performance, update mem on cache block replacement (more difficult to implement)

read = reads/program x read miss rate x read miss penalty

write = writes/program x write miss rate x write miss penalty + write buffer stall cycles

I=number of instructions

instruction miss cycles= I x .02 x 100 = 2 x I

data miss cycles=I x .36 x .04 x 100=1.44x I

total number of stalls = 3.44 x I

total CPI = 2 + 3.44 = 5.44

performance ratio = 5.44/2 = 2.72

1. direct-mapped - block address % # of blocks in cache, 1-way set

2. full associative - anywhere in cache

3. set associative - block address % # of sets in cache, n-way set

    advantages:performance is close to FA

    complexity is close to DM

write through - cache & mem, cache is always clean, when processor must wait for mem to finish write, we have a write stall

write back - cache only, write to mem occurs at replacement, less mem bandwidth used, less power used (embedded)

random

LRU (least recently used)

good but hard to implement

FIFO

block placement

block identification

block replacement

write strat

page - equivalent to "block" in cache term

- virtual page number in mem

- physical page num

page fault - equivalent to "miss" in cache term (very expensive)

pages should be large enough to amortize page fault cost (typically 4-16KB)

fully associativ organization (to reduce page faults)

page faults (handled in software, can afford clever page replacement algorithms)

write back (write-through is way too slow)

CM = 10's to 100's

PF = Millions

looking up page table = 1 mem acc

getting word = 1 mem acc

translation lookaside buffer = used for memory page hits

in the case of a tlb miss = stores valid/dirty/ref bit back to page table, much more frequent than page faults

size = 16-512 entries

block size = 1-2 page tab ent (4-8bytes)

hit time = .5-1 clock cyc

miss pen = 10-100 clock cyc

miss rate = .01%-1%

associativity = full

1. provides level of protection (user rights)

2. provides abstractions for I/O access

3. provides fair scheduling of shared I/O devices

4. types of communication

- OS can give commands to I/O dev

- I/O dev can give notif to OS

- transfer of data

behavior - input, output, storage

partner - human, machine

date rate - peak rate

streaming - data bandwidth

transactions - response time

MTBF = MTTF + MTTR

Avail = MTTF / MTBF

MTTF - fault avoidance (selection of quality, maintenance), fault tolerance (redundancy (RAID)), fault forecasting (replace component before it fails)

MTTR - better tools

platter (magnetic surface - nonvolatile storage)

tracks  (10,000 - 50,000)

sectors & gaps (512 bytes, transfer time,

error correction code)

read-write heads on Actuator arm

controller (controller time)

processor-mem bus- address, data

I/O bus - connect via proc-mem bus or backplane

graphics bus

synchronous - bus has associated clock, protocol implemented with small finite state machine, longer bus => slower, all devices run at bus speed

asynchronous - no clock (no speed, length limitations on specific devices), handshaking protocol with additional control lines