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Definition
| A method of measuring access timing to memory, which is the number of clock cycles required to write or read a column of data off a memory module. |
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Definition
| A technology used by Intel whereby the processor, chipset, and wireless network adapter are all interconnected as a unit, which improves laptop performance. |
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Definition
| A placeholder module that fills a memory slot on the motherboard when the slot does not hold a RIMM in order to maintain continuity. |
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Term
| dual inline memory module |
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Definition
| A miniature circuit board installed on a motherboard to hold memory. DIMMs can hold up to 16 GB of RAM on a single module. |
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Definition
| A memory technology by Rambus and Intel that uses a narrow network-type system bus. Memory is stored on a RIMM module. |
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Definition
| another term for Direct Rambus DRAM |
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Term
| Double Data Rate SDRAM (DDR SDRAM) |
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Definition
| A type of memory technology used on DIMMs that runs at twice the speed of the system clock. |
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Definition
| A DIMM feature whereby memory chips are installed on both sides of a DIMM. |
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Definition
A motherboard feature that improves memory performance by providing two 64-bit channels between memory and the chipset. DDR, DDR2, and DDR3 DIMMs can use dual channels.
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Definition
Two processor sockets on a server motherboard.
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Definition
| Double-sided DIMMs that provide two 64-bit banks. The memory controller accesses first one bank and then the other. These don't perform as well as single-ranked DIMMs. |
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Term
| ECC (error-correcting code) |
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Definition
A chipset feature on a motherboard that checks the integrity of data stored on DIMMs or RIMMs and can correct single-bit errors in a byte. More advanced schemas can detect, but not correct, double-bit errors in a byte.
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Term
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Definition
An error-checking scheme in which a ninth, or “parity,” bit is added. The value of the parity bit is set to either 0 or 1 to provide an even number of ones for even parity and an odd number of ones for odd parity.
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Term
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Definition
| An error that occurs when the number of 1s in the byte is not in agreement with the expected number. |
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