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Chapter 4 Vocabulary List 2
Chapter 4 Vocabulary List 2 Hornet Tech
14
Computer Science
9th Grade
12/01/2014

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Term
CAS Latency
Definition
A method of measuring access timing to memory, which is the number of clock cycles required to write or read a column of data off a memory module.
Term
Centrino
Definition
A technology used by Intel whereby the processor, chipset, and wireless network adapter are all interconnected as a unit, which improves laptop performance.
Term
Continuity RIMM
Definition
A placeholder module that fills a memory slot on the motherboard when the slot does not hold a RIMM in order to maintain continuity.
Term
dual inline memory module
Definition
A miniature circuit board installed on a motherboard to hold memory. DIMMs can hold up to 16 GB of RAM on a single module.
Term
Direct Rambus DRAM
Definition
A memory technology by Rambus and Intel that uses a narrow network-type system bus. Memory is stored on a RIMM module.
Term
Direct RDRAM
Definition
another term for Direct Rambus DRAM
Term
Double Data Rate SDRAM (DDR SDRAM)
Definition
A type of memory technology used on DIMMs that runs at twice the speed of the system clock.
Term
double-sided
Definition
A DIMM feature whereby memory chips are installed on both sides of a DIMM.
Term
dual channels
Definition

 

A motherboard feature that improves memory performance by providing two 64-bit channels between memory and the chipset. DDR, DDR2, and DDR3 DIMMs can use dual channels.

 

Term
dual processors
Definition

 

Two processor sockets on a server motherboard.

 

Term
dual ranked
Definition
Double-sided DIMMs that provide two 64-bit banks. The memory controller accesses first one bank and then the other.  These don't perform as well as single-ranked DIMMs.
Term
ECC (error-correcting code)
Definition

 

A chipset feature on a motherboard that checks the integrity of data stored on DIMMs or RIMMs and can correct single-bit errors in a byte. More advanced schemas can detect, but not correct, double-bit errors in a byte.

 

Term
Parity
Definition

 

An error-checking scheme in which a ninth, or “parity,” bit is added. The value of the parity bit is set to either 0 or 1 to provide an even number of ones for even parity and an odd number of ones for odd parity.

 

Term
parity error
Definition
An error that occurs when the number of 1s in the byte is not in agreement with the expected number.
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