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CIS CHAPTER 4
VOCABULARY
35
Computer Science
Undergraduate 1
02/01/2012

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Term
ARITHMETIC LOGIC UNIT (ALU)
Definition
A CPU COMPONENT THAT PERFORMS MATHEMATICAL FUNCTIONS ON DATA SOTRED IN THE REGISTER AREA
Term
ASSEBLY LANGUAGE
Definition
A LOW-LEVEL LANGUAGE IN WHICH A CPU'S INSTRUCTION SET IS WRITTEN
Term
BUS UNIT
Definition
THE NETWORK CIRCUITRY THAT CONNECTS ALL THE OTHER MAJOR COMPONETS TOGETHER, ACCEPT DATA, AND SENDS DATA THROUGH THE INPUT AND OUTPUT BUS SECTIONS
Term
CACHE
Definition
A SMALL TEMPORARY MEMORY AREA THAT IS USED TO SEPARATE AND STORE INCOMING DATA AND INSTRUCTIONS
Term
CLOCK DOUBLING
Definition
RUNNING THE CPU AT A MULTIPLE OF THE BUS FREQUENCY
Term
COMPILER
Definition
A SPECIAL PROGRAM THAT TRANSLATES THE HIGHER-LEVEL LANGUAGE INTO MACHINE LANUGAGE BASE ON THE CPU's INSTRUCTION SET
Term
COMPLEX INSTRUCTION SET COMPUTER (CISC)
Definition
A CPU WITH A COMPLEX INSTRUCITON SET
Term
CONTROL UNIT
Definition
A CPU COMPONENTS THAT CONTROLS THE OVERALL OPERATION OF THE CCPU
Term
DECODE UNIT
Definition
A CPU COMPONENT THAT DECODES INSTRUCTIONS AND DATA AND TRANSMITS THE DATA TO OTHER AREAS IN AN UNDERSTANDABLE FORMAT
Term
DUAL INDEPENDENT BUS
Definition
A BUS SYSTEM ARCHITECTURE IN WHICH ONE BUS CONNECTS TO THE MAIN MEMORY AND THE OTHER CONNECTS WITH THE L2 CACHE
Term
DYNAMIC EXECUTION
Definition
A TERM COINED BY INTEL TO DESCRIBE THE ENHANCED, THE SUPERSCALAR AND THE MULTIPLE BRANCH PREDICTION FEATURES ASSOCIATED WITH THE PENTIUM II PROCESSOR
Term
FRONT SIDE BUS
Definition
ANOTHER TERM FOR LOCAL BUS
Term
INSTRUCTION SET
Definition
A SET OF BASIC COMMANDS THAT CONTROL THE PROCESSOR
Term
INSTRUCTIONS
Definition
COMMANDS GIVEN TO THE PROCESSOR
Term
L1 CACHE
Definition
A CACHE CONTAINED WITHIN THE PROCESSOR THAT IS DESIGNED TO RUN AT THE PROCESSOR'S SPEED
Term
L2 CACHE
Definition
A CACHE MOUNTED OUTSIDE OF THE PROCESSORS. (NOTE:THE PENTIUM III INCORPORATES THE L2 IN THE PROCESSOR)
Term
L3 CACHE
Definition
THE CACHE MOUNTED ON THE MOTHERBOARD WHEN L1 AND L2 CACHES ARE INCORPORATED INTO THE CPU
Term
MATH COPROCESSOR
Definition

 

A COMPONENTS OF THE CPU THAT IMPROVES THE PROCESSOR'S ABLITY TO PERFORM ADVANCED MATHEMATICAL CALCULATIONS

Term
MMX PROCESSOR
Definition
A PROCESSOR WITH AN ADDITIONAL 56 COMMANDS THAT ENHANCE ITS ABILITES TO SUPPORT MULTMEDIA TECHNOLOGY
Term
MULTIPLE BRANCH PREDICTION
Definition
A TECHNIQUE THAT PREDICTS WHAT DATA ELEMENT WILL BE NEEDED NEXT, RATHER THAN WAITING FOR THRE NEXT COMMAND TO BE ISSUED
Term
OVERCLOCKING
Definition
FORCING A PROCESSOR TO OPERATE FASTER THAN ITS APPROVED SPEED
Term
PIN GRID ARRAY (PGA)
Definition
THE PATTERN OF PINS ON A CPU
Term
PROCESSOR AFFINITY
Definition
THE ABLITY TO SELECT THE NUMBER OF CPU CORES TO APPLY TO A SOFTWARE APPLICATION
Term
PROCESSOR THROTTLING
Definition
CONTROLLING PORCESSOR FREQUENCY TO CONSERVE BATTERY LIFE AND PRODUCE LESS HEAT
Term
PROTECTED MODE
Definition
AN OPERATING MODE THAT SUPPORTS MULTITASKIN AND ALLOWS ACCESS TO MEMORY BEYOND THE 1 MB
Term
REAL MODE
Definition
AN OPERATING MODE IN WHICH ONLY THE FIRST 1MB OF A SYSTEM'S RAM CAN BE ACCESSED. ALSO, AN OPERATIONG MODE IN WHICH THE 286 OR LATER PROCESSORS EMULATES AN 8088 OR 8086 PROCESSOR
Term
REDUCED INSTRUCTION SET COMPUTER (RISC)
Definition
A TYPE OF CPU ARCHITECTURE THAT IS DESIGNED WITH A FEWER NUMBER OF TRANSISTOR AND COMMANDS
Term
REGISTER UNIT
Definition
A CPU COMPONENT CONNTAINING MANY SEPARATE, SMALLER UNITS KNOWN AS REGISTERS
Term
REGISTERS
Definition
SMALL POCKETS OF MEMORY WITHIN THE PROCESSOR THAT ARE USED TO TEMPORARILY STORE DATA BEING PROCESSED BY THE CPU
Term
SIMULTANEOUS THREADING
Definition
EXECUTING TWO OR MORE THREADS AT THE SAME TIME
Term
SUPERCALAR
Definition
PROCESSING MULTIIPLE INSTRUCITONS SIMULTANEOUSLY
Term
SYSTEM MAMAGEMENT MODE (SMM)
Definition
A STANDBY MODE DEVELOPED FOR LAPTOP COMPUTERS TO SAVE ELECTICAL ENERGY WHEN USING THE BATTERY
Term
THREAD
Definition
PART OF A SOFTWARE PROGRAM THAT CAN BE EXECUTED INDEPENDENTLY OF THE ENTIRE PROGRAM
Term
VIRTUAL MODE
Definition
AN OPERATIONAL MODE IN WHICH THE PROCESSOR CAN OPERATE SEVERAL REAL MODE PROGRAMS AT ONCE AND ACCESS MEMORY HIGHER THAT THE FIRST 1MB
Term
ZERO INSERTION FORCE(ZIF) SOCKET
Definition
A PROCESSOR SOCKET EQUIPPED WITH A LEVER TO ASSIST IN THE INSTALLATION OF THE CPU
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